OR2C04A 데이터 시트보기 (PDF) - Lattice Semiconductor
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OR2C04A Datasheet PDF : 192 Pages
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Data Sheet
January 2002
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 50. Series 2 Asynchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
WR, CS0, and CS1 Pulse Width
TWR
100
D[7:0] Setup Time
TS
20
D[7:0] Hold Time
TH
0
RDY Delay
TRDY
—
RDY Low
TB
1
Earliest WR After RDY Goes High*
TWR2
0
RD to D7 Enable/Disable
TDEN
—
CCLK to DOUT
TD
—
Max
Unit
—
ns
—
ns
—
ns
60
ns
8
CCLK Periods
—
ns
60
ns
30
ns
* This parameter is valid whether the end of not RDY is determined from the RDY/RCLK pin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input D[7:0].
D[6:0] timing is the same as the write data port of the D7 waveform because D[6:0] are not enabled.
CS0
CS1
WR
D7
RD
TWR
TS
TH
WRITE DATA
TWR2
TDEN
TDEN
RDY
CCLK
DOUT
PREVIOUS BYTE
TB
TRDY
TD
D7
D0
D1
D2
D3
Figure 68. Asynchronous Peripheral Configuration Mode Timing Diagram
Lattice Semiconductor
5-4533.a
163
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