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OR2C04A

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

January 2002

ORCA Series 2 FPGAs

Timing Characteristics (continued)

Table 52A. OR2CxxA/OR2TxxA Slave Serial Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C

Parameter

Symbol

Min

Max

Unit

DIN Setup Time

TS

20

—

ns

DIN Hold Time

TH

0

—

ns

CCLK High Time

TCH

50

—

ns

CCLK Low Time

TCL

50

—

ns

CCLK Frequency

FC

—

10

MHz

CCLK to DOUT

TD

—

30

ns

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.

Table 52B. OR2TxxB Slave Serial Configuration Mode Timing Characteristics

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

DIN Setup Time

TS

15

—

ns

DIN Hold Time

TH

0

—

ns

CCLK High Time

TCH

12.5

—

ns

CCLK Low Time

TCL

12.5

—

ns

CCLK Frequency

FC

—

40

MHz

CCLK to DOUT

TD

—

10

ns

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN

DIN

CCLK

TD

DOUT

BIT N

TS

TH

TCL

TCH

BIT N

Figure 70. Slave Serial Configuration Mode Timing Diagram

5-4535(F)

Lattice Semiconductor

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