OR2C04A 데이터 시트보기 (PDF) - Lattice Semiconductor
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OR2C04A Datasheet PDF : 192 Pages
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ORCA Series 2 FPGAs
Data Sheet
January 2002
Timing Characteristics (continued)
Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
D[7:0] Setup Time
TS
20
D[7:0] Hold Time
TH
0
CCLK High Time
TCH
50
CCLK Low Time
TCL
50
CCLK Frequency
FC
—
CCLK to DOUT
TD
—
Max
—
—
—
—
10
30
Unit
ns
ns
ns
ns
MHz
ns
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
D[7:0] Setup Time
TS
15
D[7:0] Hold Time
TH
0
CCLK High Time
TCH
12.5
CCLK Low Time
TCL
12.5
CCLK Frequency
FC
—
CCLK to DOUT
TD
—
Max
—
—
—
—
40
10
Unit
ns
ns
ns
ns
MHz
ns
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
CCLK
INIT
TINIT_CLK
D[7:0]
DOUT
RDY
BYTE 0
TCH
TCL
TH
TS
BYTE 1
TD
0
1
2
3
4
5
6
7
Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram
0
5-4534(F)
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