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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

Memory Mode

The Series 4 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port RAM. A block diagram of a

PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory

and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM.

F5[A:D]

KZ[3:0]

CIN(WA1)

READ

4

ADDRESS[4:0]

DQ

5 WRITE

ADDRESS[4:0]

DIN7(WA3)

DQ

DIN5(WA2)

DQ

DIN3(WA1)

DQ

DIN1(WA0)

DQ

READ 4

DATA[3:0]

DIN6(WD3)

DQ

4 WRITE

DATA[3:0]

DIN4(WD2)

DQ

F6

F4

F2

F0

D Q Q6

D Q Q4

D Q Q2

D Q Q0

DIN2(WD1)

DQ

DIN0(WD0)

DQ

CE0, LSR0

(SEE NOTE 2.)

CE1

CLK[0:1]

DQ

S/E

WRITE

ENABLE

RAM CLOCK

1. CLK[0:1] are commonly connected in memory mode.

2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled).

CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1.

LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.

Lucent Technologies Inc.

Figure 12. Memory Mode

5-5969(F)a

19

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