VRS1000 데이터 시트보기 (PDF) - Unspecified
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VRS1000 Datasheet PDF : 47 Pages
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VRS1000
VERSA
Datasheet Rev 1.6
Description of Peripherals
System Control Register
The register represented in the next table is used for
system control. Bit 7 indicates if the system has been
reset due to the overflow of the Watch Dog Timer. It is
for this reason that users should check the WDR bit
whenever an unpredicted reset occurs.
The IAPE bit is used to enable and disable the IAP
function. When set to 1, the XRAME bit allows the user
to enable the on-chip expanded 768 bytes of RAM. Bit
0 of this register is the ALE output inhibit bit. Setting
this bit to 1 will inhibit the Fosc/6Hz clock signal output
to the ALE pin.
TABLE 15: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7
6
5
4
3
2
WDR
Unused
IAPE
1
XRA
ME
0
ALEI
Bit Mnemonic Description
7
WDR
This is the Watch Dog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
6
Unused
-
5
Unused
-
4
Unused
-
3
Unused
-
2
IAPE
IAP function enable bit
1
XRAME
768 byte on-chip enable bit
0
ALEI
ALE output inhibit bit, which is used to
reduce EMI.
Power Control Register
The VRS1000 provides two power saving modes: Idle
and Power Down. These two modes serve to reduce
the power consumption of the device.
In Idle mode, the processor is stopped but the
oscillator is still running. The content of the RAM, I/O
state and SFR registers are maintained. Timer
operation is maintained, as well as the external
interrupts.
This mode is useful for applications in which stopping
the processor to save power is required. The
processor will be woken up when an external event,
triggering an interrupt, occurs.
In Power Down mode, the oscillator of the VRS1000 is
stopped. This means that all the peripherals are
disabled. The content of the RAM and the SFR
registers, however, is maintained.
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 16: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6
5
4
3
2
Unused
1
RAMS1
0
RAMS0
Bit Mnemonic Description
7 SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3 GF1
General Purpose Flag
2 GF0
General Purpose Flag
1 PDOWN Power down mode control bit
0 IDLE
Idle mode control bit
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