VRS1000 데이터 시트보기 (PDF) - Unspecified
부품명
상세내역
제조사
VRS1000 Datasheet PDF : 47 Pages
| |||
VRS1000
VERSA
Datasheet Rev 1.6
FIGURE 13: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD
CLK
T1 Pin
÷12
0 C/T =0
1 C/T=1
Co nt ro l
TL1
0
7
Re loa d
TR1
GATE
INT0 PIN
0
7
TH1
TF1
INT
Mode 3
In Mode 3 the Timer 1 is blocked as if its control bit,
TR1, was set to 0. In this mode, Timer 0’s registers
TL0 and TH0 are configured as two separate 8-bit
counters. Also, the TL0 counter uses Timer 0’s control
bits C/T, GATE, TR0, INT0, TF0 and the TH0 counter
is held in Timer Mode (counting machine cycles) and
gains control over TR1 and TF1 from Timer 1. At this
point, TH0 controls the Timer 1 interrupt.
FIGURE 14: TIMER/COUNTER 0 MODE 3
TH0
0
CLK
CLK
T0PI N
TR0
GATE
INT0 PIN
Cont rol
TR1
TF1
÷12
0 C/T =0
TL0
0
CL K
1 C/T =1
Cont rol
TF0
7
INTERRUPT
7
INTERRUPT
Timer 2
Timer 2 of the VRS1000 is a 16-bit Timer/Counter.
Similar to timers 0 and 1, Timer 2 can operate either as
an event counter or as a timer. The user may switch
functions by writing to the C/T2 bit located in the
T2CON special function register. Timer 2 has three
operating modes: “Auto-Load” “Capture”, and “Baud
Rate Generator”. The T2CON SFR configures the
modes of operation of Timer 2. The table below
describes each bit in the T2CON special function
register.
TABLE 23: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H
7
6
5
4
3
2
TF2 EXF2 RCLK TCLK EXEN2 TR2
1
C/T2
0
CP/RL2
Bit Mnemonic Description
7
TF2
Timer 2 Overflow Flag: Set by an overflow
of Timer 2 and must be cleared by
software. TF2 will not be set when either
RCLK =1 or TCLK =1.
6
EXF2
Timer 2 external flag change in state occurs
when either a capture or reload is caused
by a negative transition on T2EX and
EXEN2=1. When Timer 2 is enabled,
EXF=1 will cause the CPU to Vector to the
Timer 2 interrupt routine. Note that EXF2
must be cleared by software.
5
RCLK
Serial Port Receive Clock Source.
1: Causes Serial Port to use Timer 2
overflow pulses for its receive clock in
modes 1 and 3.
4
TCLK
0: Causes Timer 1 overflow to be used for
the Serial Port receive clock.
Serial Port Transmit Clock.
1: Causes Serial Port to use Timer 2
overflow pulses for its transmit clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the Serial Port transmit clock.
3
EXEN2
Timer 2 External Mode Enable.
1: Allows a capture or reload to occur as a
result of a negative transition on T2EX if
Timer 2 is not being used to clock the Serial
Port.
0: Causes Timer 2 to ignore events at
T2EX.
2
TR2
Start/Stop Control for Timer 2.
1: Start Timer 2
0: Stop Timer 2
1
Timer or Counter Select (Timer 2)
C/T2
1: External event counter falling edge
triggered.
0: Internal Timer (OSC/12)
0
Capture/Reload Select.
CP/RL2
1: Capture of Timer 2 value into RCAP2H,
RCAP2L is performed if EXEN2=1 and a
negative transitions occurs on the T2EX
pin. The capture mode requires RCLK and
TCLK to be 0.
0: Auto-reload reloads will occur either with
Timer 2 overflows or negative transitions at
T2EX when EXEN2=1. When either RCK
=1 or TCLK =1, this bit is ignored and the
timer is forced to auto-reload on Timer 2
overflow.
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
19
Share Link: 