ACS8522 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8522

Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

Semtech Corporation 

ACS8522 SETS LITE

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

There are two ways to enable Fast External Switching

completely automatically. Forced Control can be invoked

mode:

z Mode enable by register write - by writing to Reg. 48

Bit 4, or

z Mode enable by hardware “initialization” - by holding

SRCSW High throughout reset and for at least a

further 251 ms after PORB has gone High (250 ms

allowance for the internal reset to be removed plus

1 ms allowance for APLLs to start-up and become

stable). A simple external circuit to set SCRSW high for

the required period is shown in “Simplified Application

Schematic” on page 114. If SCRSW pin is held Low at

any time during the 251 ms initialization period, this

may result in Fast External Switching mode not being

enabled correctly.

Once Fast External Switching mode is enabled, then the

value of the SRCSW pin directly selects either SEC1

(SRCSW High) or SEC2 (SRCSW Low). If this mode is

enabled by hardware initialization, then it configures the

default frequency tolerance of SEC1 and SEC2 to

± 80 ppm (Reg. 41 and Reg. 42). Either of these registers

can be subsequently reconfigured by external software, if

required.

When Fast External Switching mode is enabled, the

device operates as a simple switch. All clock monitoring is

by configuration, allowing transitions to be performed

under external control. This is not the normal mode of

operation, but is provided for special occasions such as

testing, or where a high degree of hands-on control is

required.

Free-run Mode

The Free-run mode is typically used following a power-on-

reset or a device reset before network synchronization

has been achieved. In the Free-run mode, the timing and

synchronization signals generated from the ACS8522 are

based on the 12.800 MHz clock frequency provided from

the external oscillator and are not synchronized to an

input reference source. By default, the frequency of the

output clock is a fixed multiple of the frequency of the

external oscillator, and the accuracy of the output clock is

equal to the accuracy of the oscillator. However the

external oscillator frequency can be calibrated to improve

its accuracy by a software calibration routine using

register cnfg_nominal_frequency (Reg. 3C and 3D). For

example a 500 ppm offset crystal could be made to look

like one accurate to within ±0.02 ppm.

The transition from Free-run to Pre-locked occurs when

the ACS8522 selects a reference source.

disabled and the DPLL will simply be forced to try to lock

on to the indicated reference source. Consequently the

device will always indicate “locked” state in the

sts_operating register (Reg. 09, Bits 2:0).

Output Clock Phase Continuity on Source

Switchover

If either PBO is selected on (default), or, if DPLL frequency

limit is set to less than ±30 ppm or (±9.2 ppm default), the

device will always comply with GR-1244-CORE[19]

specification for Stratum 3 (maximum rate of phase

change of 81 ns/1.326 ms), for all input frequencies.

Modes of Operation

Pre-locked Mode

The ACS8522 will enter the Locked state in a maximum of

100 seconds, as defined by GR-1244-CORE[19]

specification, if the selected reference source is of good

quality. If the device cannot achieve lock within 100

seconds, it reverts to Free-run mode and another

reference source is selected.

Locked Mode

The Locked mode is entered from Pre-locked, Pre-locked2

or Phase-lost mode when an input reference source has

been selected and the DPLL has locked. The DPLL is

considered to be locked when the phase loss/lock

detectors (See“Phase Lock/Loss Detection” on page 19)

The ACS8522 has three primary modes of operation

(Free-run, Locked and Holdover) supported by three

secondary, temporary modes (Pre-locked, Lost-phase and

Pre-locked2). These are shown in the State Transition

indicate that the DPLL has remained in phase lock

continuously for at least one second. When the ACS8530

is in Locked mode, the output frequency and phase tracks

that of the selected input reference source.

Diagram, Figure 4.

The ACS8522 can operate in Forced or Automatic control.

On reset, the ACS8522 reverts to Automatic Control,

where transitions between states are controlled

Lost-phase Mode

Lost-phase mode is used whenever the phase loss/lock

detectors (See“Phase Lock/Loss Detection” on page 19)

Revision 5/November 2006 © Semtech Corp.

Page 14

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