ACS8522 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8522

Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

Semtech Corporation 

ACS8522 SETS LITE

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

indicate that the DPLL has lost phase lock. The DPLL will z Fast - (Reg. 40 Bit 6, cnfg_holdover_modes,

still be trying to lock to the input clock reference, if it

exists. If the Leaky Bucket Accumulator calculates that

fast_averaging: set High), giving a -3 dB filter

response point corresponding to a period of

the anomaly is serious, the device disqualifies the

reference source. If the device spends more than 100

seconds in Lost-phase mode, the reference is disqualified

and a phase alarm is raised on it. If the reference is

disqualified, one of the following transitions takes place:

approximately eight minutes, or

z Slow - (Reg. 40 Bit 6, cnfg_holdover_modes,

fast_averaging: set Low) giving a -3 dB filter response

point corresponding to a period of approximately 110

minutes.

1. Go to Pre-locked2;

- If a known good stand-by source is available.

2. Go to Holdover;

- If no stand-by sources are available.

Holdover Mode

Instantaneous

In Instantaneous mode, the DPLL freezes at the frequency

it was operating at the time of entering Holdover mode. It

does this by using only its internal DPLL integral path

value (as reported in Reg. 0C, 0D, and 07) to determine

output frequency. The DPLL proportional path is not used

Holdover mode is the operating condition the device

enters when its currently selected input source becomes

invalid, and no other valid replacement source is

available. In this mode, the device resorts to using stored

frequency data, acquired when the input reference source

was still valid, to control its output frequency.

In Holdover mode, the ACS8522 provides the timing and

synchronization signals to maintain the Network Element

but is not phase locked to any input reference source. Its

output frequency is determined by an averaged version of

the DPLL frequency when last in the Locked Mode.

Holdover can be configured to operate in either:

z Automatic mode

(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set

Low), or

z Manual mode

(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set

High).

so that any recent phase disturbances have a minimal

effect on the Holdover frequency. The integral value used

can be viewed as a filtered version of the locked output

frequency over a short period of time. The period being in

inverse proportion to the DPLL bandwidth setting.

Manual Mode

(Reg. 34 Bit 4, cnfg_input_mode, man_holdover set

High.) The Holdover frequency is determined by the value

in register cnfg_holdover_frequency (Reg. 3E, Reg. 3F,

and part of Reg. 40). This is a 19-bit signed number, with

a LSB resolution of 0.0003068 ppm, which gives an

adjustment range of ±80 ppm. This value can be derived

from a reading of the register

sts_current_DPLL_frequency (Reg. 0D, 0C and 07), which

gives, in the same format, an indication of the current

output frequency deviation, which would be read when

the device is locked. If required, this value could be read

by external software and averaged over time. The

averaged value could then be fed to the

Automatic Mode

cnfg_holdover_frequency register, ready for setting the

averaged frequency value when the device enters

In Automatic mode, the device can be configured to

operate using either:

z Averaged - (Reg. 40 Bit 7, cnfg_holdover_modes,

auto_averaging: set High), or

Holdover mode. The sts_current_DPLL_frequency value

is internally derived from the Digital Phase Locked Loop

(DPLL) integral path, which represents a short-term

average measure of the current frequency, depending on

the locked loop bandwidth (Reg. 67) selected.

z Instantaneous - (Reg. 40 Bit 7, cnfg_holdover_modes,

auto_averaging: set Low).

Averaged

In the Averaged mode, the frequency (as reported by

It is also possible to combine the internal averaging filters

with some additional software filtering. For example the

internal fast filter could be used as an anti-aliasing filter

and the software could further filter this before

sts_current_DPLL_frequency, see Reg. 0C, Reg. 0D and

Reg. 07) is filtered internally using an Infinite Impulse

Response filter, which can be set to either:

determining the actual Holdover frequency. To support

this feature, a facility to read out the internally averaged

frequency has been provided.

Revision 5/November 2006 © Semtech Corp.

Page 15

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