FDS5672 데이터 시트보기 (PDF) - Fairchild Semiconductor
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FDS5672 Datasheet PDF : 12 Pages
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SABER Electrical Model
REV June 2005
ttemplate FDS5672 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,cjo=1.6e-9,m=0.55,tt=1.8e-8,xti=3.0)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=6.0e-10,isl=10.0e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.35,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.93,kp=50,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.82,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
DPLCAP 5
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5) 10
c.ca n12 n8 = 7e-10
RSLC1
c.cb n15 n14 = 7e-10
c.cin n6 n8 = 2.2e-9
51
RSLC2
ISCL
LDRAIN
DRAIN
2
RLDRAIN
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 67
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
GATE
1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
-
LGATE
ESG
6
8
+
EVTHRES
+ 19 -
EVTEMP
8
RGATE + 18 - 6
9
20 22
RLGATE
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
RSOURCE
DBODY
LSOURCE
SOURCE
3
RLSOURCE
l.lgate n1 n9 = 1.23e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.18e-9
S1A
12 13
8
S2A
14
15
13
S1B
S2B
res.rlgate n1 n9 = 12.3
res.rldrain n2 n5 = 10
CA
13
CB
+
+ 14
res.rlsource n3 n7 = 1.8
EGS
6
8
EDS
5
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
-
-
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=7e-4,tc2=-1.3e-7
res.rdrain n50 n16 = 1e-3, tc1=1e-4,tc2=1e-5
res.rgate n9 n20 = 1.4
res.rslc1 n5 n51 = 1e-6, tc1=1e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.2e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}
©2005 Fairchild Semiconductor Corporation
10
FDS5672 Rev. A
www.fairchildsemi.com
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