IS25F011A 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS25F011A

1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE

Integrated Silicon Solution 

IS25F011A

IS25F021A

IS25F041A

ISSI ®

Transfer Program Buffer to SRAM

The Transfer Program Buffer to SRAM command (55H)

provides access to the 264-Byte Program Buffer. The

command sequence is similar to the Write or Read SRAM

commands except that the sector address field S[15:0]

and byte address B[15:0] field are replaced with all 0 bits.

After the last byte address is transferred, the command is

completed by issuing 16 control clocks and then asserting

Transfer Program

Buffer to SRAM

Command 16 Clocks

16 Clocks

16 Clocks

SI

55H

0000H

0000H

0000H

CS high. There is a delay time after CS is asserted high

(see tXP timing specification). During this time the data

1 from the Program Buffer is being transferred to the SRAM

and neither are available for use. Status of this operation

can be checked by testing the Transfer in Process bit (TR)

in the status register. This command cannot be used while

the device is busy.

2

Transfer Time

(tXP)

3

SO

4

CONFIGURATION AND STATUS

COMMANDS

5

Read Configuration Register

The Read Configuration Register command provides

access to the configuration register, which stores the

current configuration of the HOLD-R/B pin, read clock

edge, write protect range, and alternate oscillator fre-

quency (Figure 6). The command sequence is similar to

the Read from Sector command except that the sector

address field S[15:0] and the byte-address field B[15:0]

6 are replaced with all 0 bits. After 16 control clocks and

after the Ready/Busy status field has been clocked

through, a 16-bit Configuration Data field CF[15:0] pro-

vides the contents of the Configuration Register.

7 Although the field is 16-bits long, only bits CF[8:0] are

used. All other upper bits are reserved for future

features.

Read Configuration

Register

Command 16 Clocks 16 Clocks 16 Clocks

8

SI

8BH

0000H

0000H

0000H

SO

*The CF Register only uses bits [8:0]

RB[15:0]

CF{15:0}*

9

Read/Busy

Status

Read Configuration Bits

10

11

12

Integrated Silicon Solution, Inc.

17

PRELIMINARY SF001-1A

06/24/98

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