DJLXT971ALC.A4 데이터 시트보기 (PDF) - Intel

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DJLXT971ALC.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Table 2. LXT971A MII Signal Descriptions (Continued)

PBGA LQFP

Pin# Pin#

Symbol

Type1

Signal Description

MII Control Interface Pins

D3

3 MDDIS

Management Disable. When MDDIS is High, the MDIO is disabled

from read and write operations.

I

When MDDIS is Low at power-up or reset, the Hardware Control

Interface pins control only the initial or “default” values of their

respective register bits. After the power-up/reset cycle is complete,

bit control reverts to the MDIO serial channel.

E7

43 MDC

I

Management Data Clock. Clock for the MDIO serial data channel.

Maximum frequency is 8 MHz.

D8

42 MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel

for PHY/STA communication.

A1

64 MDINT

Management Data Interrupt. When Register bit 18.1 = 1, an active

OD Low output on this pin indicates status change. Interrupt is cleared

by reading Register 19.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

Table 3. LXT971A Network Interface Signal Descriptions

PBGA

Pin#

LQFP

Pin#

Symbol

Type1

Signal Description

Twisted-Pair/Fiber Outputs, Positive & Negative.

H2

19 TPFOP

During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive

O 802.3 compliant pulses onto the line.

H3

20 TPFON

During 100BASE-FX operation, TPFOP/N pins produce differential

LVPECL outputs for fiber transceivers.

H4

23 TPFIP

H5

24 TPFIN

G2

26 SD/TP

Twisted-Pair/Fiber Inputs, Positive & Negative.

During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive

I differential 100BASE-TX or 10BASE-T signals from the line.

During 100BASE-FX operation, TPFIP/N pins receive differential

LVPECL inputs from fiber transceivers.

Signal Detect2: Dual function input depending on the state of the

device.

Reset and Power-Up. Media mode selection:

I

Tie High for FX mode (Register bit 16.0 = 1)

Tie Low for TP mode (Register bit 16.0 = 0)

Normal Operation (FX Mode): SD input from the fiber transceiver.

Normal Operation (TP Mode): Tie to GND (uses an internal pull-

down).

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

2. For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an

LVPECL logic High (2.4 V).

Datasheet

17

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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