DJLXT971ALC.A4 데이터 시트보기 (PDF) - Intel

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DJLXT971ALC.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Table 4. LXT971A Miscellaneous Signal Descriptions

PBGA

Pin#

LQFP

Pin#

Symbol Type1

Signal Description

Tx Output Slew Controls 0 and 1. These pins select the TX

output slew rate (rise and fall time) as follows:

TxSLEW1 TxSLEW0 Slew Rate (Rise and Fall Time)

TxSLEW0

D1

5

TxSLEW1

I

0

0

3.0 ns

D2

6

0

1

3.4 ns

1

0

3.9 ns

1

1

4.4 ns

Reset. This active Low input is OR’ed with the control

C2

4

RESET

I

register Reset bit (Register bit 0.15). The LXT971A reset

cycle is extended to 258 µs (nominal) after reset is de-

asserted.

G1

16

ADDR4

I

F1

15

ADDR3

I

F2

14

ADDR2

I Address <4:0>. Sets device address.

E2

13

ADDR1

I

E1

ADDR0

I

12

H1

17

RBIAS

AI

Bias. This pin provides bias current for the internal circuitry.

Must be tied to ground through a 22.1 kΩ, 1% resistor.

H8

33

PAUSE

I

Pause. When set High, the LXT971A advertises Pause

capabilities during auto-negotiation.

Sleep. When set High, this pin enables the LXT971A to go

H7

32

SLEEP

I into a low-power sleep mode. The value of this pin can be

overridden by Register bit 16.6 when in managed mode.

E8

39

PWRDWN

I

Power Down. When set High, this pin puts the LXT971A in a

power-down mode.

Crystal Input and Output. A 25 MHz crystal oscillator circuit

B1

1

REFCLK/XI

I can be connected across XI and XO. A clock can also be

C1

2

XO

O used at XI. Refer to “Clock Requirements” on page 26 in the

Functional Description section.

B7, C7

9, 10

N/C

D7

44

-

No Connection. These pins are not used and should not be

terminated.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.

18

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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