M95040-SBN3T 데이터 시트보기 (PDF) - STMicroelectronics

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M95040-SBN3T

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

Figure 9. Write Disable (WRDI) Sequence

M95040, M95020, M95010

S

01234567

C

Instruction

D

High Impedance

Q

AI03790D

Write Disable (WRDI)

One way of resetting the Write Enable Latch

(WEL) bit is to send a Write Disable instruction to

the device.

As shown in Figure 9, to send this instruction to the

device, Chip Select (S) is driven Low, and the bits

of the instruction byte are shifted in, on Serial Data

Input (D).

The device then enters a wait state. It waits for a

the device to be deselected, by Chip Select (S) be-

ing driven High.

The Write Enable Latch (WEL) bit, in fact, be-

comes reset by any of the following events:

– Power-up

– WRDI instruction execution

– WRSR instruction completion

– WRITE instruction completion

– Write Protect (W) line being held Low.

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