MT46H16M32LF 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M32LF

Mobile Low-Power DDR SDRAM

Micron Technology 

512Mb: x16, x32 Mobile LPDDR SDRAM

Ball Descriptions

Ball Descriptions

The ball descriptions table is a comprehensive list of all possible balls for all supported

packages. Not all balls listed are supported for a given package.

Table 3: Ball Descriptions

Symbol

CK, CK#

Type

Input

CKE

CKE0, CKE1

Input

CS#

CS0#, CS1#

Input

RAS#, CAS#, WE#

UDM, LDM (x16)

DM[3:0] (x32)

Input

Input

BA0, BA1

Input

A[13:0]

Input

TEST

DQ[15:0] (x16)

DQ[31:0] (x32)

LDQS, UDQS (x16)

DQS[3:0] (x32)

TQ

VDDQ

Input

Input/

output

Input/

output

Output

Supply

Description

Clock: CK is the system clock input. CK and CK# are differential clock inputs. All ad-

dress and control input signals are sampled on the crossing of the positive edge of CK

and the negative edge of CK#. Input and output data is referenced to the crossing of

CK and CK# (both directions of the crossing).

Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals,

input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-down

and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row active in

any bank). CKE is synchronous for all functions except SELF REFRESH exit. All input

buffers (except CKE) are disabled during power-down and self refresh modes.

CKE0 is used for a single LPDDR product.

CKE1 is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for ex-

ternal bank selection on systems with multiple banks. CS# is considered part of the

command code.

CS0# is used for a single LPDDR product.

CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered.

Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is

sampled on both edges of DQS. Although DM balls are input-only, the DM loading is

designed to match that of DQ and DQS balls.

Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA0 and BA1 also determine which mode reg-

ister is loaded during a LOAD MODE REGISTER command.

Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ or WRITE commands, to select one loca-

tion out of the memory array in the respective bank. During a PRECHARGE command,

A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selec-

ted by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE REGISTER command. The maximum address range is dependent

upon configuration. Unused address balls become RFU.

Test pin: Must be tied to VSS or VSSQ in normal operations.

Data input/output: Data bus for x16 and x32.

Data strobe: Output with read data, input with write data. DQS is edge-aligned with

read data, center-aligned in write data. It is used to capture data.

Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.

DQ power supply.

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN

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© 2009 Micron Technology, Inc. All rights reserved.

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