MT9160AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9160AN1

ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)

Zarlink Semiconductor Inc 

MT91L60/61

Data Sheet

PWRST/Software Reset (Rst)

While the MT91L60/61 is held in PWRST no device control or functionality is possible. While in software reset

(Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low

or by performing a hardware PWRST. While the Rst bit is high, the other bits in Control Register 1 are held low and

cannot be reprogrammed. Therefore to modify Control Register 1 the Rst bit must first be written low, followed by a

2nd write operation which writes the desired data. This avoids a race condition between clearing the reset bit and

the writing of the other bits in Control Register 1.

After a Power-up reset (PWRST) or software reset (Rst) all control bits assume their "Power Reset Value" default

states; µ-Law coding, 0 dB Rx and 6dB Tx gains and the device powered up in SSI mode 2048 kb/s operation with

Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active,

during the defined channel.

To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control

Register 1, address 03h) or set the PWRST pin low.

00

RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1

01

-

-

-

-

-

STG2 STG1

02

-

-

-

03

PDFDI PDDR RST

04

CEN

DEN

D8

05

C7

C6

C5

-

-

-

-

-

TxMute RxMute TxBsel

A/µ

Smag/ CSL2 CSL1

ITU-T

C4

C3

C2

C1

06

D7

D6

D5

D4

D3

D2

D1

07

-

-

-

-

PCM/ loopen

-

ANALOG

Table 2 - 3V Multi-featured Codec Register Map

Note: Bits marked "-" are reserved bits and should be written with logic "0"

TxFG0

Gain Control

Register 1

STG0

Gain Control

Register 2

DrGain Path Control

RxBsel Control Register 1

CSL0 Control Register 2

C0

C-Channel

Register

D0

D-Channel

Register

-

Loop Back

13

Zarlink Semiconductor Inc.

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