MT9160AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
부품명
상세내역
제조사
MT9160AN1 Datasheet PDF : 33 Pages
| |||
MT91L60/61
Data Sheet
Path Control
ADDRESS = 02h WRITE/READ VERIFY
-
-
-
-
-
-
- DrGain
7
6
5
4
3
2
1
0
Power Reset Value
XX00 0000
DrGain
When high, the receive path is summed with the side tone path and is attenuated by 6dB.
When low, the receive path contains no side tone (default).
Control Register 1
PDFDI PDDR Rst
7
6
5
ADDRESS = 03h WRITE/READ VERIFY
_ TxMute RxMute TxBsel RxBsel
Power Reset Value
0000 0000
4
3
2
1
0
PDFDI
PDDR
Rst
TxMute
RxMute
TxBsel
RxBsel
When high, the FDI PLA and the Filter/Codec are powered down (default). When low, the FDI is active.
When high, the ear driver and Filter/Codec are powered down (default). In addition, in ST-BUS mode, the selected output channel
is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will be tri-stated
outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/Codec are active if
PDFDI is low.
When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the Rst bit remains
high and device remains powered up. A software reset can be removed only by writing this bit low or by means of a hardware reset
(PWRST). This bit is useful for quickly programming the Registers to the default Power Reset Values. When this bit is low, the
reset condition is removed allowing the registers to be modified
When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a mute state
(only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When low the full transmit
path functions normally (default).
When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a mute state.
When low the full receive path functions normally (default).
When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in ST-BUS
mode. Not used in SSI mode.
When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in ST-BUS
Note: Bits marked "-" are reserved bits and should be written with logic "0"
17
Zarlink Semiconductor Inc.
Share Link: 