MT9160AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9160AN1

ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)

Zarlink Semiconductor Inc 

MT91L60/61

Data Sheet

Control Register 2

ADDRESS = 04h WRITE/READ VERIFY

CEn

DEn

D8

A/µ

Smag/

ITU-T

CSL2 CSL1 CSL0

7

6

5

4

3

2

1

0

Power Reset Value

0000 0010

CEn

DEn

D8

A/µ

Smag/ITU-T

When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the

channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h)

regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation.

When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo.

The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on

DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has

significance only for ST-BUS mode and is ignored for SSI operation.

When high, D-channel operates at 8 kb/s. When low, D-channel operates at 16 kb/s (default).

When high, A-Law encoding/decoding is selected for the MT91L60/61. When low, µ-Law encoding/decoding is selected.

When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is

selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate digit inversion (A-Law).

CSL2

1

1

1

0

0

0

0

CSL1

1

0

0

0

0

1

1

CSL0

1

0

1

0

1

0

1

Bit Clock rate (kHz)

N/A

128

256

512

1536

2048

4096

CLOCKin (kHz)

4096

4096

4096

512

1536

2048

4096

Mode

ST-BUS

SSI

SSI

SSI

SSI

SSI (default)

SSI

Note: Bits marked "-" are reserved bits and should be written with logic "0"

18

Zarlink Semiconductor Inc.

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