MT9160AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT9160AN1 Datasheet PDF : 33 Pages
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MT91L60/61
Data Sheet
C-Channel Register
ADDRESS = 05h WRITE/READ
C7 C6 C5 C4 C3 C2 C1 C0
7
6
5
4
3
2
1
0
Power Reset Value
1111 1111- write
XXXX XXXX - read
Micro-port access to the ST-BUS C-Channel information read and write
D-Channel Register
D7 D6 D5 D4
7
6
5
4
D3 D2 D1 D0
3
2
1
0
ADDRESS = 06h WRITE/READ
Power Reset Value
1111 1111- write
XXXX XXXX - read
D7-D0
Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h). Received D-
Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are accessible only when IRQ
indicates valid access.
Loopback Register
ADDRESS = 07h WRITE/READ VERIFY
-
-
-
-
PCM/ loopen
-
ANALOG
-
Power Reset Value
XXXX 0000
7
6
5
4
3
2
1
0
PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low.
For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on Din is
looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to HSPKR ±) still
functions. When low, the device is configured for analog-to-analog operation. An analog input signal at M± is looped back to the
SPKR± outputs through the A/D and D/A circuits as well as through the normal transmit A/D path (from M± to Dout).
loopen
When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit. When low,
loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
HSPKR +/-
Din
HSPKR +/-
Dout
M +/-
Dout
Analog Loopback
PCM/ANALOG = 0 loopen = 1
Digital Loopback
PCM/ANALOG = 1 loopen = 1
Figure 10 - Loopback Signal Flow
19
Zarlink Semiconductor Inc.
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