HTG2150(2000) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HTG2150
(Rev.:2000)

8-Bit 320 Pixel LCD Microcontroller

Holtek Semiconductor 

Preliminary

HTG2150

Functional Description

Execution flow

The system clock for the HTG2150 is derived

from an RC oscillator. The system clock is inter-

nally divided into four non-overlapping clocks.

One instruction cycle consists of four system

clock cycles.

Instruction fetching and execution are pipelined in

such a way that a fetch takes one instruction cycle

while decoding and execution takes the next in-

struction cycle. However, the pipelining scheme

causes each instruction to effectively execute in one

cycle. If an instruction changes the program coun-

ter, two cycles are required to complete the instruc-

tion.

Program counter - PC

The 13-bit program counter (PC) controls the

sequence in which the instructions stored in the

program ROM are executed and its contents

specify a maximum of 8192 addresses.

After accessing a program memory word to

fetch an instruction code, the contents of the

program counter are incremented by one. The

program counter then points to the memory

word containing the next instruction code.

When executing a jump instruction, conditional

skip execution, loading PCL register, subrou-

tine call, initial reset, internal interrupt, exter-

nal interrupt or return from subroutine, the PC

manipulates the program transfer by loading

the address corresponding to each instruction.

The conditional skip is activated by instruction.

Once the condition is met, the next instruction,

fetched during the current instruction execu-

tion, is discarded and a dummy cycle replaces it

to get the proper instruction. Otherwise pro-

ceed with the next instruction.

The lower byte of the program counter (PCL) is

a readable and writeable register (06H).

Moving data into the PCL performs a short

jump. The destination will be within 256 loca-

tions.

When a control transfer takes place, an addi-

tional dummy cycle is required.

Program memory - ROM

The program memory, which contains execut-

able program instructions, data and table infor-

mation, is composed of a 16384 x 16 bit format.

However as the PC (program counter) is com-

prised of only 13 bits, the remaining 1 ROM ad-

dress bit is managed by dividing the program

memory into 2 banks, each bank having a range

between 0000H and 1FFFH. To move from the

present ROM bank to a different ROM bank,

the higher 1 bit of the ROM address are set by

the BP (Bank Pointer), while the remaining 13

bits of the PC are set in the usual way by exe-

cuting the appropriate jump or call instruction.

As the full 14 address bits are latched during

the execution of a call or jump instruction, the

correct value of the BP must first be setup be-

fore a jump or call is executed. When either a

software or hardware interrupt is received,

note that no matter which ROM bank the pro-

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

S y s te m

C lo c k

PC

PC

PC +1

PC +2

F e tc h IN S T (P C )

E x e c u te IN S T (P C -1 )

F e tc h IN S T (P C + 1 )

E x e c u te IN S T (P C )

F e tc h IN S T (P C + 2 )

E x e c u te IN S T (P C + 1 )

Execution flow

1 3 b its

P ro g ra m

C o u n te r

S ta c k

B ank0

B ank1

0000H

1FFFH

8 1 9 2 ´1 6

B its

2000H

3FFFH

B a n k P o in te r

R e g is te r B it5

R O M A d d re s s

A 1 3 b it L a tc h

L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n

1 6 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e

7

July 24, 2000

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