MSM80C88A-10GS-K 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM80C88A-10GS-K Datasheet PDF : 37 Pages
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¡ Semiconductor
MSM80C88A-10RS/GS/JS
TEST
TEST: Input
This line is examined by a "WAIT" instruction.
When TEST is high, the CPU enters an idle cycle.
When TEST is low, the CPU exits in an idle cycle.
NMI
NON MASKABLE INTERRUPT: Input
This line causes a type 2 interrupt.
NMI is not maskable.
This signal is internally synchronized and needs 2-clock cycle pulse width.
RESET
RESET:Input
This signal causes the CPU to initialize immediately.
This signal is active high and must be at least four clock cycles.
CLK
CLOCK: Input
This signal provides the basic timing for the internal circuit.
MN/MX
MINIMUM/MAXIMUM: Input
This signal selects the CPU’s operating mode.
When VCC is connected, the CPU operates in minimum mode.
When GND is connected, the CPU operates in maximum mode.
VCC
VCC: +5V supplied.
GND
GROUND
The following pin function descriptions are for maximum mode only. Other pin functions are
already described.
SO, S1, S2
STATUS: Output
These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to
generate all memory and I/O access control signals. These lines are high impedance during
hold acknowledge. These status lines are encoded as shown below.
S2
S1
0 (LOW) 0
0
0
0
1
0
1
1 (HIGH) 0
1
0
1
1
1
1
S0
Characteristics
0
Interrupt acknowledge
1
Read I/O Port
0
Write I/O Port
1
Halt
0
Code Access
1
Read Memory
0
Write Memory
1
Passive
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