MSM80C88A-10GS-K 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM80C88A-10GS-K

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C88A-10RS/GS/JS

STATIC OPERATION

The MSM80C88A-10 circuitry is of static design. Internal registers, counters and latches are

static and require no refresh as with dynamic circuit design. This eliminates the minimum

operating frequency restriction placed on other microprocessors. The MSM80C88A-10 can

operate from DC to the appropriate upper frequency limit. The processor clock may be stopped

in either state (high/low) and held there indefinitely. This type of operation is especially useful

for system debug or power critical applications.

The MSM80C88A-10 can be signal stepped using only the CPU clock. This state can be

maintained as long as is necessary. Signal step clock operation allows simple interface circuitry

to provide critical information for bringing up your system.

Static design also allows very low frequency operation (down to DC). In a power critical

situation, this can provide extremely low power operation since 80C88A power dissipation is

directly related to operating frequency. As the system frequency is reduced, so is the operating

power until, ultimately, at a DC input frequency, the MSM80C88A-10 power requirement is the

standby current (500 mA maximum).

FUNCTIONAL DESCRIPTION

General Operation

The internal function of the MSM80C88A-10 consists of a Bus interface Unit (BIU) and an

Execution Unit (EU). These units operate mutually but perform as separate processors.

The BIU performs instruction fetch and queueing, operand fetch, DATA read and write address

relocation and basic bus control. By performing instruction prefetch while waiting for decoding

and execution of instruction, the CPU’s performance is increased. Up to 4-bytes for instruction

stream can be queued.

EU receives pre-fetched instructions from the BIU queue, decodes and executes instructions

and provides an un-relocated operand address to the BIU.

Memory Organization

The MSM80C88A-10 has a 20-bit address to memory. Each address has 8-bit data width.

Memory is organized 00000H to FFFFFH and is logically divided into four segments: code, data,

extra data and stack segment. Each segment contains up to 64 Kbytes and locates on a 16-byte

boundary. (Fig. 3a)

All memory references are made relative to a segment register according to a select rule.

Memory location FFFF0H is the start address after reset, and 00000H through 003FFH are

reserved as an interrupt pointer. There are 256 types of interrupt pointer:

Each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a

16-bit offset address.

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