S3C1840
REGISTER DESCRIPTIONS
Stack Register (SR)
Three levels of subroutine nesting are supported by a three-level stack as shown in Figure 1-12.
Each subroutine call (CALL) pushes the next PA and PC address into the stack. The latest stack to be stored will
be overwritten and lost. Each return instruction (RET) pops the stack back into the PA and PC registers.
SR
PA
PC
: Push Operation (CALL)
: Pop Operation (RET)
Figure 1-12. Stack Operations
Page Address Register (PA), Page Buffer Register (PB)
The Page Address Register (PA) and Page Buffer Register (PB) are 4-bit registers. The PA always specifies the
current page.
A page select instruction (PAGE #n) loads the value "n" into the PB. When JP or CALL instruction is executed,
and if the Status Flag (SF) is set to 1, the contents of PB are loaded into PA. If SF is "0", however, the JP or
CALL is executed like NOP instruction and SF is set to "1". The contents of PB don't be loaded. Figure 1-13
illustrates this concept.
4
PB
4
PA
Common Bus
PAGE #n
JP xxx (CALL xxx)
; PB n
; PA PB
if SF = 1
Figure 1-13. PA, PB Operations
1-11