S3C1840
Internal HALT
Power-on Reset
Internal HALT
Internal P2.0
CLR
Auto-Reset Counter
CLK
fxx
System Reset
The Auto-Reset Counter is cleared every 131,072/fxx (288 msec if fxx is 455 KHz).
Figure 1-19. Auto Reset Block Diagram
OSC DIVIDE OPTION CIRCUIT
The OSC Divide Option Circuit provides a maximum 1MHz fxx system clock. fOSC which is generated in
oscillation circuit is divided eight or non-divide in this circuit to produce fxx. This dividing ratio will be chosen by
mask option. (See Figure 1-20)
fOSC : Oscillator clock
fxx : System clock (fOSC or fOSC /8)
fCPU: CPU clock (fCPU = fxx/6)
1 instruction cycle clock
XI
fOSC
OSC
DIVIDE-8
XO
fXX
Mask Option
Figure 1-20. S3C1840 OSC Divide Option Circuit
1-18