S3C1860 데이터 시트보기 (PDF) - Samsung
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S3C1860 Datasheet PDF : 91 Pages
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S3C1840
Arithmetic Logic Unit (ALU), Accumulator (A)
The SMCS-51 CPU contains an ALU and its own 4-bit register (accumulator) which is the source and destination
register for most I/O, arithmetic, logic, and data memory access operations.
Arithmetic functions and logical operations will set the status flag (SF) to "0" or "1".
Status Latch (SL)
The Status latch (SL) flag is an 1-bit flip-flop register. Only the "CPNE L,A" instruction can change the value of
SL.
If the result of a "CPNE L,A" instruction is true, the SL is set to "1"; If not true, to "0".
Status Flag : SF
The Status Flag (SF) is a 1-bit flip-flop register which enables programs to conditionally skip an instruction. All
instructions, including JP and CALL, are executed when SF is "1".
But if SF is "0", the program executes NOP instruction instead of JP or CALL and resets SF to "1". Then,
program execution proceeds. The following instructions set the SF to "0":
• Arithmetic Instructions
ADDS
ADDS
INCS
INCS
INCS
SUBS
DECS
DECS
DECS
A, #n
A,@HL
A,2HL
A
L
A,@HL
A,@HL
A
L
; if no carry
; if no carry
; if no carry
; if no carry
; if no carry
; if no carry
; if no carry
; if no carry
; if no carry
• Compare Instructions
CPNE
CPNZ
CPNE
CPNE
CPNE
CPNZ
CPBT
@HL,A
@HL
L,#n
L,A
A,@HL
P0
@HL,b
• Data Transfer Instructions
MOV
MOV
@HL+,A
@HL_,A
• Logical Instructions
NOTI
A
; if M(H,L) = (A)
; if M(H,L) = 0
; if (L) = #
; if (L) = (A)
; if (A) > M(H,L)
; if (P0) = 0
; if M (H,L,b) ≠ 1
; if no carry
; if borrow
; if (A) ≠ 0 after operation
1-12
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