S3C24A0A 데이터 시트보기 (PDF) - Samsung

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S3C24A0A

32-BIT RISC MICROPROCESSOR

Samsung 

Table of Contents (Continued)

Chapter 17 USB Host Controller

Overview ....................................................................................................................................................... 17-1

USB Host Controller Special Registers ........................................................................................................ 17-2

OHCI Registers for USB Host Controller ............................................................................................. 17-2

Chapter 18 USB Device

Overview ....................................................................................................................................................... 18-1

Feature................................................................................................................................................. 18-1

USB Device Special Registers ..................................................................................................................... 18-3

FUNC_ADDR_REG ............................................................................................................................. 18-5

Power Management Register (PWR_REG) ........................................................................................ 18-6

Interrupt Register (EP_INT_REG, USB_INT_REG) ............................................................................ 18-7

Interrupt Enable Register (EP_INT_EN_REG, USB_INT_REG)......................................................... 18-9

Frame Number Register (FPAME_NUM1_REG, FRAME_NUM2_REG) ........................................... 18-10

Index Register (INDEX_REG).............................................................................................................. 18-11

End Point0 Control Status Register (EP0_CSR) ................................................................................. 18-12

End Point in Control Status Register (IN_CSR1_REG, IN_CSR2_REG) ........................................... 18-13

End Point Out Control Status Register (OUT_CSR1_REG, OUT_CSR2_REG) ................................ 18-15

End Point FIFO Register (EPN_FIFO_REG)....................................................................................... 18-17

Max Packet Register (MAXP_REG) .................................................................................................... 18-17

End Point Out Write Count Register (OUT_FIFO_CNT1_REG, OUT_FIFO_CNT2_REG) ................ 18-18

DMA Interface Control Register (EPN_DMA_CON)............................................................................ 18-19

DMA Unit Counter Register (EPN_DMA_UNIT).................................................................................. 18-20

DMA FIFO Counter Register (EPN_DMA_FIFO) ................................................................................ 18-21

DMA Total Transfer Counter Register

(EPN_DMA_TTC_L, EPN_DMA_TTC_M, EPN_DMA_TTC_H) ......................................................... 18-22

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S3C24A0A MICROPROCESSOR

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