S3C24A0A 데이터 시트보기 (PDF) - Samsung

부품명

상세내역

제조사

S3C24A0A

32-BIT RISC MICROPROCESSOR

Samsung 

Table of Contents (Continued)

Chapter 20

General Purpose I/O Ports (Continued)

External Interrupt Control Register (EXTINTC1) ................................................................................. 20-10

External Interrupt Control Register (EXTINTC2) ................................................................................. 20-11

External Interrupt Filter Control Register (EINTFLTN) ........................................................................ 20-12

External Interrupt Mask Register (EINTMASK)) .................................................................................. 20-13

External Interrupt Pending Register (EINTPEND)............................................................................... 20-14

Peripheral Port Pull up Control Register (PERIPU)............................................................................. 20-15

Alive Control Register (ALIVECON) .................................................................................................... 20-16

GPIO Output Data Register (GPDAT_SLEEP).................................................................................... 20-17

GPIO Output Control Register for Sleep Mode (GPOEN_SLEEP) ..................................................... 20-17

GPIO Pull up Control Register for Sleep Mode (GPPU_SLEEP) ........................................................ 20-17

Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP0)...................................... 20-18

Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP1)...................................... 20-19

Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP0) ................................. 20-20

Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP1) ................................. 20-21

Peripheral Port Pull up Control Register for Sleep Mode (PERIPU_SLEEP)...................................... 20-22

Reset Count Compare Register (RstCnt) ............................................................................................ 20-23

General Purpose RAM Array (GPRAMn) ............................................................................................ 20-24

Chapter 21 Camera Interface

Overview ....................................................................................................................................................... 21-1

Features ............................................................................................................................................... 21-2

External Interface ................................................................................................................................. 21-2

Signal Description ................................................................................................................................ 21-2

Timing Diagram.................................................................................................................................... 21-3

External Connection Guide .................................................................................................................. 21-5

8-Bit Mode............................................................................................................................................ 21-5

16-Bit Mode.......................................................................................................................................... 21-5

Camera Interface Operation ......................................................................................................................... 21-6

Two DMA Ports .................................................................................................................................... 21-6

Clock DOMAIN..................................................................................................................................... 21-7

Frame Memory Hirerarchy ................................................................................................................... 21-8

Memory Storing Method....................................................................................................................... 21-9

Timing Diagram for Register Setting.................................................................................................... 21-10

Timing Diagram for Last IRQ ............................................................................................................... 21-11

Software Interface......................................................................................................................................... 21-11

xiv

S3C24A0A MICROPROCESSOR

Share Link: