S3C24A0A 데이터 시트보기 (PDF) - Samsung

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S3C24A0A

32-BIT RISC MICROPROCESSOR

Samsung 

Table of Contents (Continued)

Chapter 24 MPEG-4 Motion Compensation

Overview........................................................................................................................................................24-1

Feature .................................................................................................................................................24-1

MPEG-4 Motion Compensation Operation ...................................................................................................24-2

Block Diagram ......................................................................................................................................24-2

Operation Flow .....................................................................................................................................24-3

Configuration of QCIF/CIF Frame ........................................................................................................24-4

MPEG-4 Motion Compensation Special Registers .......................................................................................24-6

Previous Frame Y Start Address Register for the Encoder (MC_PFYSA_ENC) .................................24-6

MCED Frame Y Start Address Register for the Encoder (MC_MFYSA_ENC)....................................24-6

Previous Frame Y Start Address Register for the Decoder (MC_PFYSA_DEC).................................24-6

MCED Frame Y Start Address Register for the Decoder (MC_MFYSA_DEC)....................................24-6

Previous Frame Cb Start Address Register for the Encoder (MC_PFCbSA_ENC) ............................24-7

Previous Frame Cr Start Address Register for the Encoder (MC_PFCrSA_ENC) ..............................24-7

MCED Frame Cb Start Address Register for the Encoder (MC_MFCbSA_ENC) ...............................24-7

MCED Frame Cr Start Address Register for the Encoder (MC_MFCrSA_ENC).................................24-7

Previous Frame Cb Start Address Register for the Decoder (MC_PFCbSA_DEC) ............................24-8

Previous Frame Cr Start Address Register for the Decoder (MC_PFCrSA_DEC)..............................24-8

MCED Frame Cb Start Address Register for the Decoder (MC_MFCbSA_DEC) ...............................24-8

MCED Frame Cr Start Address Register for the Decoder (MC_MFCrSA_DEC).................................24-8

Motion Vector Start Address Register for the Encoder (MC_MVSA_ENC) .........................................24-9

Motion Vector Start Address Register for the Decoder (MC_MVSA_DEC) .........................................24-9

Command Register (MC_CMND).........................................................................................................24-10

Status & S/W Reset Register (MC_STAT_SWR).................................................................................24-11

Configuration Register (MC_CNFG) ....................................................................................................24-12

Image Format Register (MC_IMGFMT) ...............................................................................................24-12

S3C24A0A MICROPROCESSOR

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