LC662508A 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC662508A
SANYO -> Panasonic
LC662508A Datasheet PDF : 17 Pages
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LC662508A, 662512A, 662516A
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Parameter
Symbol
Conditions
min
typ
Operating supply voltage
Memory retention supply voltage
VDD
VDDH
VIH1
VDD
VDD: During hold mode
P2, P3 (except for the P33/HOLD pin),
P61, and P63: N-channel output transistor off
3.0
1.8
0.8 VDD
Input high-level voltage
P33/HOLD, P5, P60, P62, P9, RES, OSC1:
VIH2
N-channel output transistor off
0.8 VDD
P0, P1, P4, P5, PC, PD, PE:
VIH3
N-channel output transistor off
0.8 VDD
P2, P3 (except for the P33/HOLD pin), P5, P6, P9,
VIL1
RES, and OSC1: N-channel output transistor off
VSS
Input low-level voltage
VIL2
P33/HOLD: VDD = 1.8 to 5.5 V
VSS
P0, P1, P4, P5, PC, PD, PE, TEST:
VIL3
N-channel output transistor off
VSS
Operating frequency
fop
0.4
(instruction cycle time)
(Tcyc)
(10)
[External clock input conditions]
Frequency
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
fext
(External clock input must be selected as the
0.4
oscillator circuit option.)
Pulse width
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
textH, textL (External clock input must be selected as the
100
oscillator circuit option.)
Rise and fall times
textR, textF
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
max
5.5
5.5
13.5
VDD
VDD
0.2 VDD
0.2 VDD
0.2 VDD
4.2
(0.95)
4.2
30
Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin.
When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications. P9 port pins with CMOS output specifications cannot be used as input pins.
3. PC port pins with CMOS output specifications cannot be used as input pins.
Contact Sanyo for details on the allowable operating ranges for P4,PC, and PD pins with inverter array specifications.
Unit
V
V
V
V
V
V
V
V
MHz
(µs)
MHz
ns
ns
Note
1
2
3
2
3
No. 5997-13/17
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