LC662508A 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC662508A
SANYO -> Panasonic
LC662508A Datasheet PDF : 17 Pages
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LC662508A, 662512A, 662516A
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Parameter
Input high-level current
Input low-level current
Output high-level voltage
Value of the output pull-up resistor
Output low-level voltage
Output off leakage current
[Schmitt characteristics]
Hysteresis voltage
High-level threshold voltage
Low-level threshold voltage
[Ceramic oscillator]
Oscillator frequency
Oscillator stabilization time
[Serial clock]
Cycle time
Input
Output
Low-level and high-level Input
pulse widths
Output
Rise an fall times
Output
[Serial input]
Symbol
IIH1
IIH2
IIH3
IIL1
IIL2
VOH1
RPO
VOL1
VOL2
IOFF1
IOFF2
IOFF3
VHYS
Vt H
Vt L
fCF
fCFS
tCKCY
tCKL
tCKH
tCKR, tCKF
Conditions
P2, P3 (except for the P33/HOLD pin),
P61, and P63: VIN = 13.5 V, with the output
Nch transistor off
P0, P1, P4, P5, P6, P9, PC, TEST, RES, and
P33/HOLD (Does not apply to P61 and P63.):
VIN = VDD,
with the output Nch transistor off
PD, PE: VIN = VDD,
with the output Nch transistor off
Input ports other than PD and PE3:
VIN = VSS, with the output Nch transistor off
PD, PE: VIN = VSS,
with the output Nch transistor off
P2, P3 (except for the P33/HOLD pin),
P6, P8, P9, and PC: IOH = –1 mA
P2, P3 (except for the P33/HOLD pin),
P6, P8, P9, and PC: IOH = –0.1 mA
P0, P1, P4, P5, P7, PA, and PB
P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB,
and PC (except for the P33/HOLD pin): IOL = 1.6 mA
P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB,
and PC (except for the P33/HOLD pin): IOL = 8 mA
P2, P3, P61, P63, and PA: VIN = 13.5 V
Does not apply to P2, P3, P61, P63, P8, and PA:
VIN = VDD
P8: VIN = VSS
min
–1.0
–1.0
VDD – 1.0
VDD – 0.5
30
–1.0
P2, P3, P5, P6, P61, P9, RES, OSC1 (EXT)
OSC1, OSC2: See Figure 2. 4 MHz
See Figure 3. 4 MHz
SCK0, SCK1: With the timing of Figure 4 and
the test load of Figure 5.
0.5 VDD
0.2 VDD
0.9
2.0
0.4
1.0
Data setup time
Data hold time
[Serial output]
Output delay time
tICK
SI0, SI1: With the timing of Figure 4.
0.3
Stipulated with respect to the rising edge (↑) of
tCKI
SCK0, SCK1.
0.3
SO0, SO1: With the timing of Figure 5 and the
tCKO
test load of Figure 5. Stipulated with respect to
the falling edge (↓) of SCK0, SCK1.
typ
100
0.1 VDD
4.0
max
5.0
Unit Note
µA
1
1.0
µA
1
1.0
µA
1
µA
2
µA
2
V
3
300
kΩ
0.4
V
5
1.5
V
5
5.0
µA
6
1.0
µA
6
µA
7
V
0.8 VDD
V
0.5 VDD
V
MHz
10.0
ms
µs
Tcyc
µs
Tcyc
0.1
µs
µs
µs
0.3
µs
Continued on next page.
No. 5997-14/17
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