LC662508A 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC662508A
SANYO -> Panasonic
LC662508A Datasheet PDF : 17 Pages
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LC662508A, 662512A, 662516A
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
Unit Note
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
INT0 high and low-level pulse
widths
interrupt can be accepted, conditions under
tIOH, tIOL which the timer 0 event counter or pulse width
2
measurement input can be accepted
Tcyc
High and low-level pulse widths
INT1, INT2: Figure 6, conditions under which
for interrupt inputs other than INT0 tIIH, tIIL the corresponding interrupt can be accepted
2
Tcyc
PIN1 high and low-level
pulse widths
PIN1: Figure 6, conditions under which the
tPINH, tPINL timer 1 event counter input can be accepted
2
Tcyc
RES high and low-level
pulse widths
RES: Figure 6, conditions under which reset
tRSH, tRSL can be applied.
3
Tcyc
Operating current drain
Halt mode current drain
Hold mode current drain
IDD OP
IDDHALT
IDDHOLD
VDD: 4MHz ceramic oscillator
VDD: 4MHz external clock
VDD: 4MHz ceramic oscillator
VDD: 4MHz external clock
VDD: VDD = 1.8 to 5.5 V
4.5
8.0
mA
8
4.5
8.0
mA
2.5
5.5
mA
2.5
5.5
mA
0.01
10
µA
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins. (Also applicable when the p-channel open-drain option is specified for P8.)
4. With the output Nch transistor off for pull-up output specification pins.
5. Applies to P8 when the CMOS output specifications are selected.
6. With the output Nch transistor off for open-drain output specification pins.
7. With the output Pch transistor off for open-drain output specification pins.
8. Reset state
Tone (DTMF) Output Characteristics
DC Characteristics at Ta = –30 to +70°C, VSS = 0 V
1. When the MLOUT enable option is selected (the ML output function can be used)
Parameter
Symbol
Conditions
Tone output voltage (p-p)
Row/column tone output
voltage ratio
VT1
DBCR1
DT: Dual tone, VDD = 3.5 to 5.5 V*
DT: Dual tone, VDD = 3.5 to 5.5 V*
Tone distortion
THD1 DT: Single tone, VDD = 3.5 to 5.5 V*
Note: * See item 2. below if the MLOUT disable mask option is selected.
min
0.9
1.0
2. When the MLOUT disable option is selected (the ML output function cannot be used)
Parameter
Symbol
Conditions
Tone output voltage (p-p)
Row/column tone output
voltage ratio
VT1
DBCR1
DT: Dual tone, VDD = 3.0 to 5.5 V*
DT: Dual tone, VDD = 3.0 to 5.5 V*
Tone distortion
THD1 DT: Single tone, VDD = 3.0 to 5.5 V*
Note: * See item 1. above if the MLOUT enable mask option is selected.
min
0.9
1.0
typ
1.3
2.0
2
max
Unit
2.0
V
3.0
dB
7
%
typ
1.3
2.0
2
max
Unit
2.0
V
3.0
dB
7
%
No. 5997-15/17
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