82801IBICH9 데이터 시트보기 (PDF) - Intel
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82801IBICH9 Datasheet PDF : 885 Pages
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13.8.3.11GPE0_STS—General Purpose Event 0 Status Register .................. 512
13.8.3.12GPE0_EN—General Purpose Event 0 Enables Register .................. 515
13.8.3.13SMI_EN—SMI Control and Enable Register ................................. 517
13.8.3.14SMI_STS—SMI Status Register ................................................. 519
13.8.3.15ALT_GP_SMI_EN—Alternate GPI SMI Enable Register .................. 521
13.8.3.16ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................. 522
13.8.3.17UPRWC—USB Per-Port Registers Write Control ............................ 522
13.8.3.18GPE_CNTL— General Purpose Control Register............................ 523
13.8.3.19DEVACT_STS — Device Activity Status Register .......................... 523
13.8.3.20PM2_CNT—Power Management 2 Control (Mobile Only)................ 524
13.8.3.21C3_RES— C3 Residency Register (Mobile Only) ........................... 524
13.8.3.22C5_RES— C5 Residency Register (Mobile Only) ........................... 525
13.9 System Management TCO Registers (D31:F0) ..................................................... 526
13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 526
13.9.2 TCO_DAT_IN—TCO Data In Register ....................................................... 527
13.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 527
13.9.4 TCO1_STS—TCO1 Status Register .......................................................... 527
13.9.5 TCO2_STS—TCO2 Status Register .......................................................... 529
13.9.6 TCO1_CNT—TCO1 Control Register ......................................................... 531
13.9.7 TCO2_CNT—TCO2 Control Register ......................................................... 532
13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 532
13.9.9 TCO_WDCNT—TCO Watchdog Control Register ......................................... 533
13.9.10SW_IRQ_GEN—Software IRQ Generation Register .................................... 533
13.9.11TCO_TMR—TCO Timer Initial Value Register............................................. 533
13.10 General Purpose I/O Registers (D31:F0)............................................................. 534
13.10.1GPIO_USE_SEL—GPIO Use Select Register [31:0] .................................... 535
13.10.2GP_IO_SEL—GPIO Input/Output Select Register [31:0] ............................. 535
13.10.3GP_LVL—GPIO Level for Input or Output Register [31:0] ........................... 536
13.10.4GPO_BLINK—GPO Blink Enable Register [31:0] ........................................ 536
13.10.5GP_SER_BLINK[31:0]—GP Serial Blink [31:0] .......................................... 537
13.10.6GP_SB_CMDSTS[31:0]—GP Serial Blink Command Status [31:0]................ 538
13.10.7GP_SB_DATA[31:0]—GP Serial Blink Data [31:0] ..................................... 538
13.10.8GPI_INV—GPIO Signal Invert Register [31:0]........................................... 539
13.10.9GPIO_USE_SEL2—GPIO Use Select 2 Register [60:32] .............................. 539
13.10.10GP_IO_SEL2—GPIO Input/Output Select 2 Register [60:32] ..................... 540
13.10.11GP_LVL2—GPIO Level for Input or Output 2 Register [63:32] ................... 540
14 SATA Controller Registers (D31:F2)....................................................................... 541
14.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 541
14.1.1 VID—Vendor Identification Register (SATA—D31:F2) ................................ 542
14.1.2 DID—Device Identification Register (SATA—D31:F2) ................................. 543
14.1.3 PCICMD—PCI Command Register (SATA–D31:F2)..................................... 543
14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ......................................... 544
14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................... 545
14.1.6 PI—Programming Interface Register (SATA–D31:F2)................................. 545
14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h .......... 545
14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 546
14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 546
14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 546
14.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2) .................... 547
14.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2) ................... 547
14.1.10HTYPE—Header Type (SATA–D31:F2) ..................................................... 547
14.1.11PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2) ....................................................................... 547
14.1.12PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2).................................................................................... 548
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet
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