82801IBICH9 데이터 시트보기 (PDF) - Intel
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82801IBICH9 Datasheet PDF : 885 Pages
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14.2
14.3
14.4
14.1.13SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) ........................................................................... 548
14.1.14SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) ........................................................................... 548
14.1.15BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2) .................................................................................... 549
14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index
Data Pair Base Address (SATA–D31:F2) ................................................... 549
14.1.16.1When SCC is not 01h ............................................................... 549
14.1.16.2When SCC is 01h .................................................................... 550
14.1.17 SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ................ 550
14.1.18SID—Subsystem Identification Register (SATA–D31:F2)............................. 550
14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 550
14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 551
14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2) ........................................ 551
14.1.22 IDE_TIM — IDE Timing Register (SATA–D31:F2) ....................................... 551
14.1.23PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)........................................................................ 551
14.1.24PC—PCI Power Management Capabilities Register
(SATA–D31:F2) .................................................................................... 552
14.1.25PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)........................................................................ 552
14.1.26MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 553
14.1.27MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ......... 554
14.1.28MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 555
14.1.29MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 555
14.1.30 MAP—Address Map Register (SATA–D31:F2)............................................. 556
14.1.31 PCS—Port Control and Status Register (SATA–D31:F2) .............................. 556
14.1.32SCLKCG - SATA Clock Gating Control Register .......................................... 559
14.1.33 SCLKGC - SATA Clock General Configuration Register ................................ 560
14.1.33.1SATACR0—SATA Capability Register 0 (SATA–D31:F2) ................. 561
14.1.33.2SATACR1—SATA Capability Register 1 (SATA–D31:F2) ................. 561
14.1.34FLRCID—FLR Capability ID (SATA–D31:F2) .............................................. 562
14.1.35FLRCLV—FLR Capability Length and Version (SATA–D31:F2)....................... 562
14.1.36 FLRC—FLR Control (SATA–D31:F2) ......................................................... 563
14.1.37 ATC—APM Trapping Control Register (SATA–D31:F2)................................. 563
14.1.38 ATS—APM Trapping Status Register (SATA–D31:F2).................................. 564
14.1.39 SP Scratch Pad Register (SATA–D31:F2) .................................................. 564
14.1.40BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 565
14.1.41 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 567
14.1.42 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 567
Bus Master IDE I/O Registers (D31:F2)............................................................... 568
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 569
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................ 570
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2) ................................................................................. 571
14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................ 571
14.2.5 AIDR—AHCI Index Data Register (D31:F2)............................................... 571
Serial ATA Index/Data Pair Superset Registers ..................................................... 572
14.3.1 SINDX – Serial ATA Index (D31:F2) ........................................................ 572
14.3.2 SDATA – Serial ATA Data (D31:F2) ......................................................... 573
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) ............................. 574
14.3.2.2 PxSCTL — Serial ATA Control Register (D31:F2) .......................... 575
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)............................... 576
AHCI Registers (D31:F2) .................................................................................. 577
14.4.1 AHCI Generic Host Control Registers (D31:F2).......................................... 578
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Intel® I/O Controller Hub 9 (ICH9) Family Datasheet
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