P83C180AER/001 데이터 시트보기 (PDF) - Philips Electronics

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P83C180AER/001

Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.

Philips Electronics 

Philips Semiconductors

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

Product specification

P83Cx80; P87C380

7.3 Additional Special Function Registers

The standard SFRs as used in 80C51 and the SFRs for some typical derivative functions like I2C-bus interface, Timer,

etc. are described in the “Data Handbook IC20”. The specific SFRs for the P83C880 are introduced in the relevant

chapters. Some SFRs which are not mentioned or not dedicated to a certain function will be described in the following

sections.

All new additional SFRs used in the P83C880 are listed in Table 4. However, only some of them will be explained in detail

in Sections 7.3.1 to 7.3.7.

Table 4 Overview of additional SFRs

REGISTER

DESCRIPTION

ADDRESS RESET VALUE(1) READ/WRITE(2)

RAMBUF

DDCCON

DDCADR

DDCDAT

DFCON

ADCDAT

PWM10H

PWM10L

S1CON

S1STA

S1DAT

S1ADR

PWME1

PWME2

PWM0 to PWM9

DAC0 to DAC3

HFP

HFPOPW

MDCST

VFP

VFPOPW

PULCNT

HFHIGH

VFHIGH

VFLHFL

T2

RAM Buffer I/O Interface Register

9CH

DDC Control Register

9DH

DDC Address Pointer

9EH

Data Shift Register for DDC1

9FH

Miscellaneous Control Register

C0H

ADC Control Register

C1H

PWM High-byte Data Latch

C6H

PWM Low-byte Data Latch

C7H

Control Register for DDC2

D8H

Status Register for DDC2

D9H

Data Shift Register for DDC2

DAH

Address Register for DDC2

DBH

PWM Output Control Register 1

C8H

PWM Output Control Register 2

E8H

Data Latches for 8-bit PWMs

C9H to CFH,

EDH to EFH

8-bit Data Latches for 8-bit DACs

E9H to ECH

Free run Control Register for HSYNCout

F6H

Free run and Pulse width for HSYNCout

F7H

Mode Detect Control and Status Register

F8H

Free run Control Register for VSYNCout

F9H

Free run and Pulse width for VSYNCout

Pulse Generation Control Register

FAH

FBH

Horizontal Period Counting High-byte

Register

FCH

Vertical Period Counting High-byte Register

FDH

Vertical and Horizontal Period Counting

Low-nibbles Register

FEH

Watchdog Timer Data Register

FFH

XXXX XXXX

X00X 0000

0000 0000

0000 0000

1000 0000

XX00 0000

0000 0000

1000 0000

0000 0000

1111 1000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0110 0000

0001 1111

1X00 0000

0100 0000

XX000101

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

B

UBBU BBBB

B

B

B

UUBB BBBRO

B

B

B

Ro

B

B

B

B

B

B

B

B

BUBB RRRR

B

B

B

Ro

Ro

Ro

B

Notes

1. X = don’t care; even if it’s implemented.

2. B = both read/write and Ro = read only; accessible for the entire byte or an individual bit. U = not implemented.

1997 Dec 12

12

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