S25FL032P 데이터 시트보기 (PDF) - Cypress Semiconductor

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S25FL032P

32-Mbit 3.0 V Flash Memory

Cypress Semiconductor 

S25FL032P

3. Input/Output Descriptions

Table 1. Input/Output Descriptions

Signal

I/O

Description

SO/IO1

I/O

Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an

input pin in Dual and Quad I/O, and Quad Page Program modes.

SI/IO0

I/O

Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and

program data on SI on the rising edge of SCK. Functions as an output pin in Dual and Quad I/O mode.

SCK

Input

Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising

edge of SCK. Triggers output on SO after the falling edge of SCK.

Chip Select: Places device in active power mode when driven low. Deselects device and places SO at

CS#

Input

high impedance when high. After power-up, device requires a falling edge on CS# before any command

is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in

ign HOLD#/IO3

Des W#/ACC/IO2

ew VCC

N GND

I/O

I/O

Input

Input

progress.

Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is

at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low.

Functions as an output pin in Quad I/O mode.

Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low,

prevents any program or erase command from altering the data in the protected memory area. Functions

as an output pin in Quad I/O mode.

Supply voltage

Ground

Not Recommended for 4. Logic Symbol

VCC

SI/IO0

SCK

CS#

W#/ACC/IO2

HOLD#/IO3

GND

SO/IO1

Document Number: 002-00650 Rev. *L

Page 7 of 60

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