LC66354C 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC66354C Datasheet PDF : 21 Pages
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LC66354C, 66356C, 66358C
Continued from preceding page.
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
[Arithmetic, logic and comparison instructions]
Operation
EXL
Exclusive or M with 0 0 0 1 0 1 0 1 1 1 AC ← (AC)
AC then store AC
[M (HL)]
ANDM And M with AC then 0 0 0 0 0 0 1 1 1 1 M (HL) ← (AC)
store M
[M (HL)]
ORM
Or M with AC then
store M
0 0 0 0 0 1 0 0 1 1 M (HL) ← (AC)
[M (HL)]
Description
Affected
status
bits
Take the logical exclusive or
of AC and M (HL) and store ZF
the result in AC.
Take the logical and of AC
and M (HL) and store the
ZF
result in M (HL).
Take the logical or of AC and
M (HL) and store the result ZF
in M (HL).
Compare the contents of AC
and M (HL) and set or clear CF
and ZF according to the result.
CM
Compare AC with M 0 0 0 1 0 1 1 0 1 1 [M (HL)] + (AC) + 1
Magnitude
comparison
CF ZF ZF, CF
[M (HL)] > (AC)
[M (HL)] = (AC)
[M (HL)] < (AC)
00
11
10
Note
CI i4
Compare AC with
immediate data
Compare the contents of AC
and the immediate data
I3 I2 I1 I0 and set or clear CF
and ZF according to the result.
1100 1111
1 0 1 0 I3 I2 I1 I0 2
2 I3 I2 I1 I0 + (AC) + 1
Magnitude
comparison
I3 I2 I1 I0 > AC
I3 I2 I1 I0 = AC
I3 I2 I1 I0 < AC
CF ZF ZF, CF
00
11
10
CLI i4
Compare DPL with
immediate data
1100 1111
1 0 1 1 I3 I2 I1 I0 2
Compare AC bit with 1 1 0 0 1 1 1 1
CMB t2 M data bit
1 1 0 1 0 0 t1 t0 2
[Load and store instructions]
Load AC and E from
LAE
M2 (HL)
0101 1100 1
LAI i4
Load AC with
immediate data
1 0 0 0 I3 I2 I1 I0 1
Load AC from M
LADR i8 direct
1100 0001
I7 I6 I5 I4 I3 I2 I1 I0 2
S
Store AC to M
0100 0111 1
SAE
Store AC and E to
M2 (HL)
0101 1110 1
LA reg Load AC from
M (reg)
0 1 0 0 1 0 t0 0 1
ZF ← 1
2
if (DPL) = I3 I2 I1 I0
ZF ← 0
if (DPL) I 3 I2 I1 I0
Compare the contents of DPL
with the immediate data.
Set ZF if identical and clear ZF
ZF if not.
ZF ← 1
if (AC, t2) = [M (HL), Compare the corresponding
t2]
2 ZF← 0
bits specified by t0 and t1 in
AC and M (HL). Set ZF if
ZF
if (AC, t2) [M (HL), identical and clear ZF if not.
t2]
1
AC ← M (HL),
E ← M (HL + 1)
1 AC ← I3 I2 I1 I0
2 AC ← [M (i8)]
1 M (HL) ← (AC)
1
M (HL) ← (AC)
M (HL + 1) ← (E)
1 AC ← [M (reg)]
Load the contents of M2 (HL)
into AC, E.
Load the immediate data
into AC.
ZF
Load the contents of M (i8)
into AC.
ZF
Store the contents of AC into
M (HL).
Store the contents of AC, E
into M2 (HL).
Load the contents of M (reg)
into AC.
The reg is either HL or XY
depending on t0.
ZF
reg
T0
HL
0
XY
1
Has a vertical
skip function
Continued on next page.
No. 5484-15/21
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