NJU6631ACH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6631ACH

16-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6631A

(1-7) Timing Generator

The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal

circuits operation.

RAM read timing for the display and internal operation timing for MPU access are separately generated, so

that they may not interfere with each other.

Therefore, when the data write to the DD RAM for example, there will be no undesirable influence, such as

flickering, in areas other than the display area.

(1-8) LCD Driver

LCD driver circuits consist of 16-common driver and 40-segment driver.

The 40 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift

performed completely. This latched data controls display driver to output LCD driving waveform.

(1-9) Cursor Blinking Control Circuit

This circuits controls cursor On/Off and cursor position character blinks.

The cursor or blinks appear in the digit residing at the DD RAM address set in the address counter (AC).

When the address counter is (04)H, a cursor position is shown as follows :

AC6 AC5 AC4 AC3 AC2 AC1 AC0

AC 0 0 0 0 1 0 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ←Display Position

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ←DD RAM Address

(Hexadecimal)

Cursor Position

Note）The cursor or blinks appear when the address counter (AC) selects the CG RAM.

But the displayed the cursor and blink are meaningless.

If the AC storing the CG RAM address data, the cursor and blink are displayed in the meaningless

position.

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