CS61574A 데이터 시트보기 (PDF) - Cirrus Logic

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CS61574A

T1/E1 Line Interface

Cirrus Logic 

CS61574A CS61575

Percent of

nominal

peak

voltage

120

110

100

90

80

269 ns

244 ns

194 ns

50

10

Nominal Pulse

0

-10

-20

219 ns

488 ns

Figure 9. Mask of the Pulse at the 2048 kbps Interface

The E1 G.703 pulse shape is supported with line

length selection LEN2/1/0=0/0/0. The pulse

width will meet the G.703 pulse shape template

shown in Figure 9, and specified in Table 4.

The CS61574A and CS61575 will detect a static

TCLK, and will force TTIP and TRING low to

prevent transmission when data is not present.

When any transmit control pin (TAOS, LEN0-2

or LLOOP) is toggled, the transmitter outputs

will require approximately 22 bit periods to stabi-

lize. The transmitter will take longer to stabilize

when RLOOP is selected because the timing cir-

cuitry must adjust to the new frequency.

Transmit All Ones Select

The transmitter provides for all ones insertion at

the frequency of TCLK. Transmit all ones is se-

lected when TAOS goes high, and causes

continuous ones to be transmitted on the line

(TTIP and TRING). In this mode, the TPOS and

TNEG (or TDATA) inputs are ignored. If Remote

Loopback is in effect, any TAOS request will be

ignored.

Receiver

The receiver extracts data and clock from an AMI

(Alternate Mark Inversion) coded signal and out-

puts clock and synchronized data. The receiver is

sensitive to signals over the entire range of

ABAM cable lengths and requires no equalization

or ALBO (Automatic Line Build Out) circuits.

The signal is received on both ends of a center-

tapped, center-grounded transformer. The

transformer is center tapped on the IC side. The

clock and data recovery circuit exceeds the jitter

tolerance specifications of Publications 43802,

43801, AT&T 62411, TR-TSY-000170, and

CCITT REC. G.823.

For c oax ia l c able, For shielded twisted

75Ω loa d a nd pair, 120Ω load and

transformer specified transformer specified

in Application Section. in Application Section.

Nominal peak voltage of a mark (pulse)

2.37 V

3V

Peak voltage of a space (no pulse)

0 ±0.237 V

0 ±0.30 V

Nominal pulse width

244 ns

Ratio of the amplitudes of positive and negative

pulses at the center of the pulse interval

0.95 to 1.05*

Ratio of the widths of positive and negative

pulses at the nominal half amplitude

0.95 to 1.05*

* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 Specifications

12

DS154F2

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