CS61574A 데이터 시트보기 (PDF) - Cirrus Logic

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CS61574A

T1/E1 Line Interface

Cirrus Logic 

CS61574A CS61575

In the Hardware Mode, data at RPOS and RNEG

should be sampled on the rising edge of RCLK,

the recovered clock. In the Extended Hardware

Mode, data at RDATA should be sampled on the

falling edge of RCLK. In the Host Mode, CLKE

determines the clock polarity for which output

data should be sampled as shown in Table 5.

MODE

(pin 5)

CLKE

(pin 28)

LOW

X

(<0.2V)

HIGH

LOW

(>(V+) - 0.2V)

HIGH

HIGH

(>(V+) - 0.2V)

MIDDLE

X

(2.5V)

X = Don’t care

DATA

RPOS

RNEG

RPOS

RNEG

SDO

RPOS

RNEG

SDO

RDATA

CLOCK Clock Edge

for Valid Data

RCLK

RCLK

Rising

Rising

RCLK

RCLK

SCLK

Rising

Rising

Falling

RCLK

RCLK

SCLK

Falling

Falling

Rising

RCLK

Falling

Table 5. Data Output/Clock Relationship

Loss of Signal

The receiver will indicate loss of signal after

power-up, reset or upon receiving 175 consecu-

tive zeros. A digital counter counts received

zeros, based on RCLK cycles. A zero is received

when the RTIP and RRING inputs are below the

input comparator slicing threshold level estab-

lished by the peak detector. After the signal is

removed for a period of time the data slicing

threshold level decays to approximately

300 mVpeak.

If ACLKI is present during the LOS state, ACLKI

is switched into the input of the jitter attenuator,

resulting in RCLK matching the frequency of

ACLKI. The jitter attenuator buffers any instanta-

neous changes in phase between the last

recovered clock and the ACLKI reference clock.

This means that RCLK will smoothly transition

to the new frequency. If ACLKI is not present,

then the crystal oscillator of the jitter attenuator is

forced to its center frequency. Table 6 shows the

status of RCLK upon LOS.

Crystal

present?

No

Yes

Yes

ACLKI

present?

Yes

No

Yes

Source of RCLK

ACLKI

Centered Crystal

ACLKI via the

Jitter Attenuator

Table 6. RCLK Status at LOS

Jitter Attenuator

The jitter attenuator reduces wander and jitter in

the recovered clock signal. It consists of a 32 or

192-bit FIFO, a crystal oscillator, a set of load

capacitors for the crystal, and control logic. The

jitter attenuator exceeds the jitter attenuation re-

quirements of Publications 43802 and REC.

G.742. A typical jitter attenuation curve is shown

in Figure 12. The CS61575 fully meets AT&T

62411 jitter attenuation requirements. The

CS61574A will have a discontinuity in the jitter

transfer function when the incoming jitter ampli-

tude exceeds approximately 23 UIs.

The jitter attenuator works in the following man-

ner. The recovered clock and data are input to the

FIFO with the recovered clock controlling the

FIFO’s write pointer. The crystal oscillator con-

trols the FIFO’s read pointer which reads data out

of the FIFO and presents it at RPOS and RNEG

(or RDATA). RCLK is equivalent to the oscilla-

tor’s output. By changing the load capacitance

that the IC presents to the crystal, the oscillatior

frequency (and RCLK) is adjusted to the average

frequency of the recovered signal. Logic deter-

mines the phase relationship between the read and

write pointers and decides how to adjust the load

capacitance of the crystal. Jitter is absorbed in the

FIFO according to the jitter transfer characteristic

shown in Figure 12.

14

DS154F2

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