CS61574A 데이터 시트보기 (PDF) - Cirrus Logic

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CS61574A

T1/E1 Line Interface

Cirrus Logic 

Bits

567

000

001

010

011

100

101

110

111

Status

Reset has occurred or no program input.

TAOS in effect.

LLOOP in effect

TAOS/LLOOP in effect.

RLOOP in effect.

DPM changed state since last "clear DPM"

occurred.

LOS changed state since last "clear LOS"

occurred.

LOS and DPM have changed state since

last "clear LOS" and "clear DPM".

Table 12. Coding for Serial Output bits 5,6,7

Power Supply

The device operates from a single +5 Volt supply.

Separate pins for transmit and receive supplies

provide internal isolation. These pins should be

connected externally near the device and decou-

pled to their respective grounds. TV+ must not

exceed RV+ by more than 0.3V.

Decoupling and filtering of the power supplies is

crucial for the proper operation of the analog cir-

cuits in both the transmit and receive paths. A 1.0

µF capacitor should be connected between TV+

and TGND, and a 0.1 µF capacitor should be con-

nected between RV+ and RGND. Use mylar or

ceramic capacitors and place them as closely as

possible to their respective power supply pins. A

68 µF tantalum capacitor should be added close

to the RV+/RGND supply. Wire-wrap bread-

boarding of the line interface is not recommended

because lead resistance and inductance serve to

defeat the function of the decoupling capacitors.

CS61574A CS61575

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

Call: (512) 445-7222

DS154F2

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