ADSP-BF539F 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF539F Datasheet PDF : 68 Pages
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ADSP-BF539/ADSP-BF539F
include support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. The UART ports support two modes of
operation:
• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UARTs have two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART ports’ baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART ports’ clock rate is calculated as:
UART Clock Rate
=
-------------------f--S--C--L---K-------------------
16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general purpose timer functions, auto-
baud detection is supported on UART0.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
PROGRAMMABLE I/O PINS
The ADSP-BF539/ADSP-BF539F processor has numerous
peripherals that may not all be required for every application.
Many of the pins thus have a secondary function, as general
purpose I/O pins. There are two types of programmable I/O
pins on the ADSP-BF539/ADSP-BF539F processor, with
slightly different functionality: programmable flags and general
purpose I/O.
Programmable Flags (PFx)
The ADSP-BF539/ADSP-BF539F processor has 16 bi-direc-
tional, general purpose Programmable Flag (PF15–0) pins.
Each programmable flag can be individually controlled by
manipulation of the flag control, status and interrupt registers:
• Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.
• Flag Control and Status Registers – The ADSP-
BF539/ADSP-BF539F processor employs a “write one to
modify” mechanism that allows any combination of indi-
vidual flags to be modified in a single instruction, without
affecting the level of any other flags. Four control registers
Preliminary Technical Data
are provided. One register is written in order to set flag val-
ues, one register is written in order to clear flag values, one
register is written in order to toggle flag values, and one
register is written in order to specify a flag value. Reading
the flag status register allows software to interrogate the
sense of the flags.
• Flag Interrupt Mask Registers – The two Flag Interrupt
Mask Registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two Flag Con-
trol Registers that are used to set and clear individual flag
values, one Flag Interrupt Mask Register sets bits to enable
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be triggered by soft-
ware interrupts.
• Flag Interrupt Sensitivity Registers – The two Flag Inter-
rupt Sensitivity Registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensi-
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
General Purpose I/O
The ADSP-BF539/ADSP-BF539F has 38 general-purpose I/O
pins that are multiplexed with other peripherals. They are
arranged into ports C, D, and E, as shown in Table 4 on Page 13.
The GPIO differ from the Programmable Flags in that the GPIO
pins cannot generate interrupts to the processor.
The general purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins will
not cause interrupts to be generated to the processor, but may
be polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
• GPIO control and status registers – The ADSP-
BF539/ADSP-BF539F processor employs a “write one to
modify” mechanism that allows any combination of indi-
vidual GPIO to be modified in a single instruction, without
affecting the level of any other GPIO. Four control registers
and a data register are provided for each GPIO port. One
register is written in order to set GPIO values, one register
is written in order to clear GPIO values, one register is
written in order to toggle GPIO values, and one register is
written in order to specify a GPIO input or output. Reading
the GPIO data allows software to determine the state of the
input GPIO pins.
Note that the GP pin is used to specify the status of the GPIO
pins PC9–PC4 at power up. If GP is tied high, then pins
PC9–PC4 are configured as GPIO after reset. The pins cannot
be reconfigured through software, and special care must be
taken with the MLF pin. If the GP pin is tied low, then the pins
are configured as MXVR pins after reset, but may be reconfig-
ured as GPIO pins through software.
Rev. PrF | Page 12 of 68 | September 2006
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