ADSP-BF539F 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF539F

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

Table 4. Programmable Flag / GPIO Ports

Peripheral

PPI

SPORT0

SPORT1

SPORT2

SPORT3

SPI0

SPI1

SPI2

UART0

UART1

UART2

CAN

MXVR

TWI0

TWI1

Alternate Programmable

Flag / GPIO Port Function

PF15–0

PE7–0

PE15–8

PF7–0

PD4–0

PD9–5

PD11–10

PD13–12

PC1–0

PC9–4

PARALLEL PERIPHERAL INTERFACE

The ADSP-BF539/ADSP-BF539F processor provides a Parallel

Peripheral Interface (PPI) that can connect directly to parallel

A/D and D/A converters, video encoders and decoders, and

other general purpose peripherals. The PPI consists of a dedi-

cated input clock pin, up to 3 frame synchronization pins, and

up to 16 data pins. The input clock supports parallel data rates

up to fSCLK/2 MHz, and the synchronization signals can be con-

figured as either inputs or outputs.

The PPI supports a variety of general purpose and ITU-R 656

modes of operation. In general purpose mode, the PPI provides

half-duplex, bi-directional data transfer with up to 16 bits of

data. Up to 3 frame synchronization signals are also provided.

In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-

tional transfer of 8- or 10-bit video data. Additionally, on-chip

decode of embedded start-of-line (SOL) and start-of-field (SOF)

preamble packets is supported.

General Purpose Mode Descriptions

The General Purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input Mode – Frame Syncs and data are inputs into the

PPI.

• Frame Capture Mode – Frame Syncs are outputs from the

PPI, but data are inputs.

• Output Mode – Frame Syncs and data are outputs from the

PPI.

ADSP-BF539/ADSP-BF539F

Input Mode

This mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_Count register. Data widths of 8, 10, 11, 12, 13, 14, 15 and

16-bits are supported, as programmed by the PPI_CONTROL

register.

Frame Capture Mode

This mode allows the video source(s) to act as a slave (e.g., for

frame capture). The ADSP-BF539/ADSP-BF539F processor

controls when to read from the video source(s). PPI_FS1 is an

HSYNC output and PPI_FS2 is a VSYNC output.

Output Mode

This mode is used for transmitting video or other data with up

to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

• Active Video Only Mode

• Vertical Blanking Only Mode

• Entire Field Mode

Active Video Only Mode

This mode is used when only the active video portion of a field

is of interest and not any of the blanking intervals. The PPI will

not read in any data between the End of Active Video (EAV)

and Start of Active Video (SAV) preamble symbols, or any data

present during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are fil-

tered by the PPI. After synchronizing to the start of Field 1, the

PPI will ignore incoming samples until it sees an SAV code. The

user specifies the number of active video lines per frame (in

PPI_Count register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. The MXVR supports synchronous

Rev. PrF | Page 13 of 68 | September 2006

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