ADSP-BF539F 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF539F

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to

the beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader is pro-

vided that adds additional booting mechanisms. This secondary

loader provides the capability to boot from 16-bit flash memory,

fast flash, variable baud rate, and other sources. In all Boot

modes except Bypass, program execution starts from on-chip L1

memory address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU plus

two load/store plus two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

DEVELOPMENT TOOLS

The ADSP-BF539/ADSP-BF539F processor is supported with a

complete set of CROSSCORE®† software and hardware develop-

ment tools, including Analog Devices emulators and

Preliminary Technical Data

VisualDSP++®‡ development environment. The same emulator

hardware that supports other Blackfin processors also fully

emulates the ADSP-BF539/ADSP-BF539F processor.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to processor assembly. The processor

has architectural features that improve the efficiency of com-

piled C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory,

and stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

† CROSSCORE is a registered trademark of Analog Devices, Inc.

‡ VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. PrF | Page 18 of 68 | September 2006

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