ADSP-BF539F 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

ADSP-BF539F

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

Threads, Critical and Unscheduled regions, Semaphores,

Events, and Device flags. The VDK also supports Priority-based,

Preemptive, Cooperative, and Time-Sliced scheduling

approaches. In addition, the VDK was designed to be scalable. If

the application does not use a specific feature, the support code

for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the graphi-

cal and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-BF539/ADSP-BF539F processor to

monitor and control the target board processor during emula-

tion. The emulator provides full speed emulation, allowing

inspection and modification of memory, registers, and proces-

sor stacks. Non intrusive in-circuit emulation is assured by the

use of the processor’s JTAG interface—the emulator does not

affect target system loading or timing.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the Blackfin processor family. Hard-

ware tools include Blackfin processor PC plug-in cards. Third

party software tools include DSP libraries, real time operating

systems, and block diagram design tools.

DESIGNING AN EMULATOR COMPATIBLE

PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG processor. The emulator

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

ADSP-BF539/ADSP-BF539F

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-

erence on the Analog Devices web site (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

EXAMPLE CONNECTIONS AND LAYOUT

CONSIDERATIONS

Figure 9 shows an example circuit connection of the ADSP-

BF539/ADSP-BF539F connecting to a MOST network. This

diagram is intended as an example and exact connections and

recommended circuit values should be obtained from Analog

Devices.

VOLTAGE REGULATOR LAYOUT GUIDELINES

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1-0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the ADSP-

BF539/ADSP-BF539F as possible.

For further details on the on-chip voltage regulator and related

board design guidelines, see the EE-228: Switching Regulator

Design Considerations for ADSP-BF533 Blackfin Processors

applications note on the Analog Devices web site (www.ana-

log.com)—use site search on “EE-228”.

MXVR BOARD LAYOUT GUIDELINES

MLF pin

• Capacitors:

C1: 0.1μF (PPS type, 2% tolerance recommended)

C2: 0.01μF (PPS type, 2% tolerance recommended)

• Resistor:

R1: 220 ohm (1% tolerance)

• The RC network connected to the MLF pin should be

located physically close to the MLF pin on the board.

• The RC network should be wired up and connected to the

MLF pin using wide traces.

• The capacitors in the RC network should be grounded to

MXEGND.

• The RC network should be shielded using MXEGND

traces.

• Avoid routing other switching signals near the RC network

to avoid crosstalk.

Rev. PrF | Page 19 of 68 | September 2006

Share Link: