ADSP-BF538 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF538 Datasheet PDF : 56 Pages
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ADSP-BF538/ADSP-BF538F
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The Power Savings Factor is calculated as:
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.8 V to
1.2V(–5%/+10%) from an external 2.7 V to 3.6 V supply.
Figure 6 shows the typical external components required to
complete the power management system.† The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while I/O power (VDDRTC, V ) DDEXT is still supplied.
While in hibernate mode, I/O power is still being applied, elimi-
nating the need for external buffers. The voltage regulator can
be activated from this power-down state either through an RTC
wakeup, a CAN wakeup, a general-purpose wakeup, or by
asserting RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
Preliminary Technical Data
Alternatively, because the ADSP-BF538/ADSP-BF538F proces-
sors include an on-chip oscillator circuit, an external crystal
may be used. The crystal should be connected across the CLKIN
and XTAL pins, with two capacitors connected as shown in
Figure 7. Capacitor values are dependent on crystal type and
should be specified by the crystal manufacturer. A parallel-reso-
nant, fundamental frequency, microprocessor-grade crystal
should be used.
CLKIN
XTAL
BLACKFIN
PROCESSOR
CLKOUT
Figure 7. External Crystal Connections
As shown in Figure 8 on Page 14, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1× to 63× multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
VDDEXT
VDDINT
100 µF
10 µH
2.25V - 3.6V
INPUT VOLTAGE
RANGE
100 µF 1 µF
0.1 µF
ZHCS1000
FDS9431A
VROUT1-0
EXTERNAL COMPONENTS
NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 6. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF538/ADSP-BF538F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
† See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COURSE” ADJUSTMENT
ON-THE-F LY
CLKI N
PLL
0.5x - 64x
، 1, 2, 4, 8
VCO
، 1:15
CCLK
SCLK
SCLK ≤ CCLK
SCLK ≤ 133 MHz
Figure 8. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios:
Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz)
SSEL3–0 VCO/SCLK VCO
SCLK
0001
1:1
100
100
0110
6:1
300
50
1010
10:1
500
50
Rev. PrD | Page 14 of 56 | May 2006
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