ADSP-BF538 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF538

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF538/ADSP-BF538F processor pin definitions are listed

in Table 10. In order to maintain maximum functionality and

reduce package size and pin count, some pins have dual, multi-

plexed functionality. In cases where pin functionality is

reconfigurable, the default state is shown in plain text, while

alternate functionality is shown in italics.

Table 10. Pin Descriptions

Pin Name

I/O

Function

Driver Type

Memory Interface

ADDR19–1

O

Address Bus for Async/Sync Access

A

DATA15–0

I/O

Data Bus for Async/Sync Access

A

ABE1–0/SDQM1–0

O

Byte Enables/Data Masks for Async/Sync Access

A

BR

I

Bus Request (This pin should be pulled HIGH when not used.)

BG

O

Bus Grant

A

BGH

O

Bus Grant Hang

A

Asynchronous Memory Control

AMS3–0

O

Bank Select

A

ARDY

I

Hardware Ready Control (This pin should always be pulled LOW when not used.)

AOE

O

Output Enable

A

ARE

O

Read Enable

A

AWE

O

Write Enable

A

Flash Control

FCE

I

Flash Enable (This pin should be left unconnected if not used.)

FRESET

I

Flash Reset (This pin should be left unconnected if not used.)

Synchronous Memory Control

SRAS

O

Row Address Strobe

A

SCAS

O

Column Address Strobe

A

SWE

O

Write Enable

A

SCKE

O

Clock Enable

A

CLKOUT

O

Clock Output

B

SA10

O

A10 Pin

A

SMS

O

Bank Select

A

Timers

TMR0

I/O

Timer 0

C

TMR1/PPI_FS1

I/O

Timer 1/PPI Frame Sync1

C

TMR2/PPI_FS2

I/O

Timer 2/PPI Frame Sync2

C

Two Wire Interface Port (These pins are open drain and require a pullup resistor. See version 2.1 of the I2C specification for

proper resistor values.)

SDA0

I/O 5V TWI0 Serial Data

E

SCL0

I/O 5V TWI0 Serial Clock

E

SDA1

I/O 5V TWI1 Serial Data

E

SCL1

I/O 5V TWI1 Serial Clock

E

Rev. PrD | Page 18 of 56 | May 2006

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