ADSP-BF538 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF538

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

ADSP-BF538/ADSP-BF538F

Table 10. Pin Descriptions (Continued)

Pin Name

I/O

Serial Port0

RSCLK0

I/O

RFS0

I/O

DR0PRI

I

DR0SEC

I

TSCLK0

I/O

TFS0

I/O

DT0PRI

O

DT0SEC

O

Serial Port1

RSCLK1

I/O

RFS1

I/O

DR1PRI

I

DR1SEC

I

TSCLK1

I/O

TFS1

I/O

DT1PRI

O

DT1SEC

O

SPI0 Port

MOSI0

I/O

MISO0

I/O

SCK0

I/O

UART0 Port

RX0

I

TX0

O

PPI Port

PPI3–0

I/O

PPI_CLK

I

Port C: Controller Area Network/GPIO

CANTX/PC0

I/O 5V

CANRX/PC1

I/O 5V

PC[9:4]

I/O

Port D: SPI1/SPI2/UART1/UART2/GPIO

MOSI1/PD0

I/O

MISO1/PD1

I/O

SCK1/PD2

I/O

SPI1SS/PD3

I/O

SPI1SEL/PD4

I/O

MOSI2/PD5

I/O

MISO2/PD6

I/O

Function

Driver Type

SPORT0 Receive Serial Clock

D

SPORT0 Receive Frame Sync

C

SPORT0 Receive Data Primary

SPORT0 Receive Data Secondary

SPORT0 Transmit Serial Clock

D

SPORT0 Transmit Frame Sync

C

SPORT0 Transmit Data Primary

C

SPORT0 Transmit Data Secondary

C

SPORT1 Receive Serial Clock

D

SPORT1 Receive Frame Sync

C

SPORT1 Receive Data Primary

SPORT1 Receive Data Secondary

SPORT1 Transmit Serial Clock

D

SPORT1 Transmit Frame Sync

C

SPORT1 Transmit Data Primary

C

SPORT1 Transmit Data Secondary

C

SPI0 Master Out Slave In

C

SPI0 Master In Slave Out (This pin should always be pulled HIGH through a 4.7 C

KΩ resistor if booting via the SPI port.)

SPI0 Clock

D

UART Receive

UART Transmit

C

PPI3–0

C

PPI Clock

CAN Transmit/GPIO

C

CAN Receive/GPIO

C

GPIO

SPI1 Master Out Slave In/GPIO

C

SPI1 Master In Slave Out/GPIO

C

SPI1 Clock/GPIO

D

SPI1 Slave Select Input/GPIO

C

SPI1 Slave Select Enable/GPIO

C

SPI2 Master Out Slave In/GPIO

C

SPI2 Master In Slave Out/GPIO

C

Rev. PrD | Page 19 of 56 | May 2006

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