HMS91C7134K 데이터 시트보기 (PDF) - Hynix Semiconductor

부품명

상세내역

제조사

HMS91C7134K

8-BIT SINGLE-CHIP MONITOR MICROCONTROLLERS

Hynix Semiconductor 

HMS9xC7132 / HMS9xC7134

8.4 List of SFRS

Register

Description

P0

SP

DPL

DPH

PCON

TCON

TMOD

TL0

TL1

TH0

TH1

P1

P1SFS

P2SFS

P3SFS

ADAT

ACON

P2

PWMCON

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

WDTKEY

WDTRST

IEA

IE

P3

DPWMCON

DPWM0

DPWM1

IPA

IP

T2CON

RC2L

RC2H

PSW

RAMBUF

Port0 Register

Stack Point register

Data Pointer(Low byte) Register

Data Pointer(High byte) Register

Power Control Register

Timer/Counter Control Register

Timer/Counter Mode Control Register

Timer/Counter0 Low byte Register

Timer/Counter1 Low byte Register

Timer/Counter0 High byte Register

Timer/Counter1 High byte Register

Port1 Register

Port1 Special Function Selection Register

Port2 Special Function Selection Register

Port3 Special Function Selection Register

ADC Data Register

ADC Control Register

Port2 Register

PWM Control Register

PWM0 Output Register

PWM1 Output Register

PWM2 Output Register

PWM3 Output Register

PWM4 Output Register

PWM5 Output Register

PWM6 Output Register

PWM7 Output Register

Watchdog Key Register

Watchdog Timer Reset Register

Interrupt Enable Register

Interrupt Enable Register

Port3 Register

Dynamic PWM Control Register

Dynamic PWM0 Output Register

Dynamic PWM1 Output Register

Interrupt Priority Register

Interrupt Priority Register

Timer2 Control Register

Reload Low Register

Reload High Register

Program Status Word Register

RAM Buffer I/O Interface Register

Address

80H

81H

82H

83H

87H

88H

89H

8AH

8BH

8CH

8DH

90H

91H

92H

93H

96H

97H

0A0H

0A1H

0A2H

0A3H

0A4H

0A5H

0AAH

0ABH

0ACH

0ADH

0AEH

0A6H

0A7H

0A8H

0B0H

0B1H

0B2H

0B3H

0B6H

0B8H

0C8H

0CAH

0CBH

0D0H

0D4H

Initial Value

R/W

76543210

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W x x 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W x x 0 x 0 0 0 1

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 x x x x x 0 0

R/W 0 0 0 0 0 0 0 0

R/W 1 1 1 1 1 1 1 1

R/W 0 x x x x x 0 0

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 0 x x x x x 0 0

R/W x 0 0 0 0 0 0 0

R/W 0 x x x x 0 x x

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W x x x x x x x x

20

May.2001 ver1.1

Share Link: