HMS91C7134K 데이터 시트보기 (PDF) - Hynix Semiconductor
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HMS91C7134K Datasheet PDF : 90 Pages
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HMS9xC7132 / HMS9xC7134
Timer0 and Timer1 interrupt:
•Timer0 and Timer1 interrupts are generated by TF0 and TF1
which are set by an overflow of their respective Timer/Counter
registers(except for Timer0 in mode3).
•These flags are cleared by the internal hardware.
Timer2 interrupt:
•Timer2 interrupt is generated by TF2 which is set by an overflow
of Timer2.
• This flag has to be cleared by the software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or
cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
Interrupt
Sources
INT0
MD
Timer0
I2C
INT1
DDC
Timer1
VSYNC
Not
used
Timer2
IE / IEA
IP / IPA
Priority
High
Low
Global
Enable
Figure 9-1 Interrupt system
May.2001 ver1.1
25
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