HMS9xC7132 / HMS9xC7134
9.2 Interrupt Enable structure
Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in the interrupt enable special function
register IE and IEA. All interrupt source can also be globally dis-
abled by clearing bit EA in IE.
7
6
5
4
3
2
2
0
EA
EVSYNC
ET2
ES
ET1
EX1
ET0
EX0
Table 9-1 Interrupt Enable Register(IE: 0A8H)
RESET VALUE:00000000B
BIT
SYMBOL
Disable all interrupts.
FUNCTION
7
EA
0 : no interrupt will be acknowledged
1 : each interrupt source is individually enabled or disabled by setting or clear
ing its enable bit
6
EVSYNC
Enable Vsync interrupt
5
ET2
Enable timer2 interrupt
4
ES
Not used
3
ET1
Enable timer1 interrupt
2
EX1
Enable external interrupt (INT1)
1
ET0
Enable timer0 interrupt
0
EX0
Enable external interrupt (INT0)
Table 9-2 Description of the IE bits
7
EDDC
BIT
7
6
5
4
3
2
1
0
6
5
4
3
-
-
-
-
Table 9-3 Interrupt Enable Register(IEA: 0A7H)
2
2
-
EI2C
RESET VALUE:0xxxxx00B
SYMBOL
EDDC
EX6
EX5
EX4
EX3
EX2
EI2C
EMD
Enable DDC interrupt
Not used
Not used
Not used
Not used
Not used
Enable I2C interrupt
Enable MD interrupt
FUNCTION
Table 9-4 Description of Enable Register(IEA: 0A7H)
0
EMD
26
May.2001 ver1.1