MC145170P2 데이터 시트보기 (PDF) - Freescale Semiconductor

부품명

상세내역

제조사

MC145170P2

PLL Frequency Synthesizer with Serial Interface

Freescale Semiconductor 

Pin Connections

from each pin to ground (up to a maximum of 30 pF each, including stray capacitance). An external

feedback resistor of 1.0 to 5.0 MΩ is connected directly across the pins to ensure linear operation of the

amplifier. The required connections for the components are shown in Figure 11.

5 MΩ is required across the OSCin and OSCout pins in the ac-coupled case (see Figure 9 or alternate circuit

Figure 10). OSCout is an internal node on the device and should not be used to drive any loads (i.e., OSCout

is unbuffered). However, the buffered REFout is available to drive external loads.

The external signal level must be at least 1 Vpp; the maximum frequencies are given in Table 6, the Loop

Specifications table on page 7. These maximum frequencies apply for R Counter divide ratios as indicated

in the table. For very small ratios, the maximum frequency is limited to the divide ratio times 2 MHz.

(Reason: the phase/frequency detectors are limited to a maximum input frequency of 2 MHz.)

If an external source is available which swings virtually rail-to-rail (VDD to VSS), then dc coupling can be

used. In the dc-coupled case, no external feedback resistor is needed. OSCout must be a No Connect to

avoid loading an internal node on the device, as noted above. For frequencies below 1 MHz, dc coupling

must be used. The R counter is a static counter and may be operated down to dc. However, wave shaping

by a CMOS buffer may be required to ensure fast rise and fall times into the OSCin pin. See Figure 25.

Each rising edge on the OSCin pin causes the R counter to decrement by one.

REFout

Reference Frequency Output (Pin 3)

This output is the buffered output of the crystal-generated reference frequency or externally provided

reference source. This output may be enabled, disabled, or scaled via bits in the C register (see Figure 16).

REFout can be used to drive a microprocessor clock input, thereby saving a crystal. Upon power up, the

on-chip power-on-initialize circuit forces REFout to the OSCin divided-by-8 mode.

REFout is capable of operation to 10 MHz; see the Loop Specifications table. Therefore, divide values for

the reference divider are restricted to two or higher for OSCin frequencies above 10 MHz.

If unused, the pin should be floated and should be disabled via the C register to minimize dynamic power

consumption and electromagnetic interference (EMI).

3.3 Counter Output Pins

fR

R Counter Output (Pin 9)

This signal is the buffered output of the 15-stage R counter. fR can be enabled or disabled via the C register

(patented). The output is disabled (static low logic level) upon power up. If unused, the output should be

left disabled and unconnected to minimize interference with external circuitry.

The fR signal can be used to verify the R counter's divide ratio. This ratio extends from 5 to 32,767 and is

determined by the binary value loaded into the R register. Also, direct access to the phase detector via the

OSCin pin is allowed by choosing a divide value of 1 (see Figure 17). The maximum frequency which the

phase detectors operate is 2 MHz. Therefore, the frequency of fR must not exceed 2 MHz.

MC145170-2 Technical Data, Rev. 5

Freescale Semiconductor

11

Share Link: